/* $NoKeywords:$ */ /** * @file * * AMD Family_15 P-state HPC mode Initialization * * Enables High performance Computing mode. * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU/Family/0x15 * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ * */ /* ****************************************************************************** * * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. * * AMD is granting you permission to use this software (the Materials) * pursuant to the terms and conditions of your Software License Agreement * with AMD. This header does *NOT* give you permission to use the Materials * or any rights under AMD's intellectual property. Your use of any portion * of these Materials shall constitute your acceptance of those terms and * conditions. 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Read MSRC001_0063[CurPstate] and store the value in OriginalPstate. LibAmdMsrRead (MSR_PSTATE_STS, &MsrData, StdHeader); OriginalPstate = (UINT8) (((PSTATE_STS_MSR *) &MsrData)->CurPstate); // Step2. Write 0 to MSRC001_0062[PstateCmd]. // Step3. Wait for MSRC001_0063[CurPstate] == 0. GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader); // Step4. If D18F4x15C[NumBoostStates] != D18F3xDC[PstateMaxVal], execute the following sequence // 4.A Set X = D18F4x15C[NumBoostStates]. // 4.B If X+1 == D18F3xDC[PstateMaxVal], go to step 5. // 4.C Copy MSRC001_00[6B:64] indexed by P-state X to MSRC001_00[6B:64] indexed by P-state X+1. // 4.D Write 0b to PstateEn from MSRC001_00[6B:64] indexed by P-state X+1. // 4.E Set X = X+1 and go to step B. IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); GetPciAddress (StdHeader, Socket, Module, &PciAddr, &IgnoredSts); PciAddr.Address.Function = FUNC_4; PciAddr.Address.Register = CPB_CTRL_REG; LibAmdPciRead (AccessWidth32, PciAddr, &CpbCtrl, StdHeader); // F4x15C PciAddr.Address.Function = FUNC_3; PciAddr.Address.Register = CPTC2_REG; LibAmdPciRead (AccessWidth32, PciAddr, &CPTC2, StdHeader); // F3xDC // In case that F3xDC[PstateMaxVal] was increased by Low Power Pstate function during the first time of running that function. // Get the real PstateMaxVal by checking C001_00[6B:64][PsEnable] while (CPTC2.PstateMaxVal != 0) { LibAmdMsrRead ((PS_REG_BASE + CPTC2.PstateMaxVal), &MsrData, StdHeader); if ((MsrData & BIT63) == BIT63) { break; } CPTC2.PstateMaxVal--; } if (CpbCtrl.NumBoostStates != CPTC2.PstateMaxVal) { X = (UINT8) CpbCtrl.NumBoostStates; while ((X + 1) < (UINT8) CPTC2.PstateMaxVal) { LibAmdMsrRead ((PS_REG_BASE + X), &MsrData, StdHeader); MsrData &= ~BIT63; LibAmdMsrWrite ((PS_REG_BASE + X + 1), &MsrData, StdHeader); // Make sure Agesa doesn't declared the P-states modified by these algorithms to the OS if (PStateLevelingBuffer != NULL) { PStateLevelingBufferTemp = PStateLevelingBuffer; for (i = 0; i < SocketCount; i++) { PStateLevelingBufferTemp->PStateCoreStruct[0].PStateStruct[X + 1].PStateEnable = 0; //Calculate next node buffer address PStateLevelingBufferTemp = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferTemp + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferTemp->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); } } X++; } } // Step5. Write OriginalPstate to MSRC001_0062[PstateCmd]. // Step6. Wait for MSRC001_0063[CurPstate] == OriginalPstate. FamilySpecificServices->TransitionPstate (FamilySpecificServices, OriginalPstate, (BOOLEAN) TRUE, StdHeader); // Step7. Write D18F3x64[HtcPstateLimit] with the value from D18F3xDC[PstateMaxVal] PciAddr.Address.Register = HTC_REG; LibAmdPciRead (AccessWidth32, PciAddr, &Htc, StdHeader); // F3x64 Htc.HtcPstateLimit = CPTC2.PstateMaxVal; LibAmdPciWrite (AccessWidth32, PciAddr, &Htc, StdHeader); // F3x64 return Flag; } CONST PSTATE_HPC_MODE_FAMILY_SERVICES ROMDATA F15PstateHpcSupport = { 0, F15InitializePstateHpcMode };