/* $NoKeywords:$ */ /** * @file * * Graphics Controller family specific service procedure * * * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ * */ /* ***************************************************************************** * * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. * * AMD is granting you permission to use this software (the Materials) * pursuant to the terms and conditions of your Software License Agreement * with AMD. This header does *NOT* give you permission to use the Materials * or any rights under AMD's intellectual property. Your use of any portion * of these Materials shall constitute your acceptance of those terms and * conditions. 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Use of the Materials by the * Government constitutes acknowledgement of AMD's proprietary rights in them. * * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any * direct product thereof will be exported directly or indirectly, into any * country prohibited by the United States Export Administration Act and the * regulations thereunder, without the required authorization from the U.S. * government nor will be used for any purpose prohibited by the same. * *************************************************************************** * */ /*---------------------------------------------------------------------------------------- * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */ #include "FchPlatform.h" #include "Filecode.h" /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ /*---------------------------------------------------------------------------------------- * Default FCH interface settings at InitReset phase. *---------------------------------------------------------------------------------------- */ CONST FCH_RESET_INTERFACE ROMDATA FchResetInterfaceDefault = { TRUE, // UmiGen2 TRUE, // SataEnable TRUE, // IdeEnable TRUE, // GppEnable TRUE, // Xhci0Enable TRUE // Xhci1Enable }; /*---------------------------------------------------------------- * InitReset Phase Data Block Default (Failsafe) *---------------------------------------------------------------- */ FCH_RESET_DATA_BLOCK InitResetCfgDefault = { NULL, // StdHeader {0}, // FchReset 0, // FastSpeed 0, // WriteSpeed 0, // Mode 0, // AutoMode 0, // BurstWrite FALSE, // SataIdeCombMdPriSecOpt 0, // Cg2Pll FALSE, // EcKbd FALSE, // LegacyFree FALSE, // SataSetMaxGen2 9, // SataClkMode 0, // SataModeReg FALSE, // SataInternal100Spread 2, // SpiSpeed FALSE, // EcChannel0 { // FCH_GPP { // Array of FCH_GPP_PORT_CONFIG PortCfg[4] { FALSE, // PortPresent FALSE, // PortDetected FALSE, // PortIsGen2 FALSE, // PortHotPlug 0, // PortMisc }, { FALSE, // PortPresent FALSE, // PortDetected FALSE, // PortIsGen2 FALSE, // PortHotPlug 0, // PortMisc }, { FALSE, // PortPresent FALSE, // PortDetected FALSE, // PortIsGen2 FALSE, // PortHotPlug 0, // PortMisc }, { FALSE, // PortPresent FALSE, // PortDetected FALSE, // PortIsGen2 FALSE, // PortHotPlug 0, // PortMisc }, }, PortA1B1C1D1, // GppLinkConfig FALSE, // GppFunctionEnable FALSE, // GppToggleReset 0, // GppHotPlugGeventNum 0, // GppFoundGfxDev FALSE, // GppGen2 0, // GppGen2Strap FALSE, // GppMemWrImprove FALSE, // GppUnhidePorts 0, // GppPortAspm FALSE, // GppLaneReversal TRUE, // GppPhyPllPowerDown TRUE , // GppDynamicPowerSaving FALSE, // PcieAer FALSE, // PcieRas FALSE, // PcieCompliance FALSE, // PcieSoftwareDownGrade TRUE, // UmiPhyPllPowerDown FALSE, // SerialDebugBusEnable 0, // GppHardwareDownGrade 0, // GppL1ImmediateAck TRUE, // NewGppAlgorithm 0, // HotPlugPortsStatus 0, // FailPortsStatus 40, // GppPortMinPollingTime }, NULL // OemResetProgrammingTablePtr };