/* $NoKeywords:$ */ /** * @file * * mttecc3.c * * Technology ECC byte support for registered DDR3 * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/Tech/DDR3) * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ * **/ /***************************************************************************** * * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. * * AMD is granting you permission to use this software (the Materials) * pursuant to the terms and conditions of your Software License Agreement * with AMD. This header does *NOT* give you permission to use the Materials * or any rights under AMD's intellectual property. Your use of any portion * of these Materials shall constitute your acceptance of those terms and * conditions. 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Use of the Materials by the * Government constitutes acknowledgement of AMD's proprietary rights in them. * * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any * direct product thereof will be exported directly or indirectly, into any * country prohibited by the United States Export Administration Act and the * regulations thereunder, without the required authorization from the U.S. * government nor will be used for any purpose prohibited by the same. * *************************************************************************** * */ /* *---------------------------------------------------------------------------- * MODULES USED * *---------------------------------------------------------------------------- */ #include "AGESA.h" #include "mm.h" #include "mn.h" #include "mt.h" #include "Filecode.h" CODE_GROUP (G1_PEICC) RDATA_GROUP (G1_PEICC) #define FILECODE PROC_MEM_TECH_DDR3_MTTECC3_FILECODE /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS * *---------------------------------------------------------------------------- */ /*---------------------------------------------------------------------------- * TYPEDEFS AND STRUCTURES * *---------------------------------------------------------------------------- */ /*---------------------------------------------------------------------------- * PROTOTYPES OF LOCAL FUNCTIONS * *---------------------------------------------------------------------------- */ /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * *---------------------------------------------------------------------------- */ /* -----------------------------------------------------------------------------*/ /** * * This function sets the DQS ECC timings for registered DDR3 * * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK * * @return TRUE - No fatal error occurs. * @return FALSE - Fatal error occurs. */ BOOLEAN MemTSetDQSEccTmgsRDdr3 ( IN OUT MEM_TECH_BLOCK *TechPtr ) { UINT8 Dct; UINT8 Dimm; UINT8 i; UINT8 *WrDqsDly; UINT16 *RcvEnDly; UINT8 *RdDqsDly; UINT8 *WrDatDly; UINT8 EccByte; INT16 TempValue; MEM_NB_BLOCK *NBPtr; CH_DEF_STRUCT *ChannelPtr; EccByte = TechPtr->MaxByteLanes (); NBPtr = TechPtr->NBPtr; if (NBPtr->MCTPtr->NodeMemSize) { for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { NBPtr->SwitchDCT (NBPtr, Dct); if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { ChannelPtr = NBPtr->ChannelPtr; for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm * 2))) { i = Dimm * TechPtr->DlyTableWidth (); WrDqsDly = &ChannelPtr->WrDqsDlys[i]; RcvEnDly = &ChannelPtr->RcvEnDlys[i]; RdDqsDly = &ChannelPtr->RdDqsDlys[i]; WrDatDly = &ChannelPtr->WrDatDlys[i]; // Receiver DQS Enable: // Receiver DQS enable for ECC bytelane = Receiver DQS enable for bytelane 3 - // [write DQS for bytelane 3 - write DQS for ECC] TempValue = (INT16) RcvEnDly[3] - (INT16) (WrDqsDly[3] - WrDqsDly[EccByte]); if (TempValue < 0) { TempValue = 0; } RcvEnDly[EccByte] = (UINT16) TempValue; // Read DQS: // Read DQS for ECC bytelane = read DQS of byte lane 3 // RdDqsDly[EccByte] = RdDqsDly[3]; // Write Data: // Write Data for ECC bytelane = Write DQS for ECC + // [write data for bytelane 3 - Write DQS for bytelane 3] TempValue = (INT16) (WrDqsDly[EccByte] + (INT8) (WrDatDly[3] - WrDqsDly[3])); if (TempValue < 0) { TempValue = 0; } WrDatDly[EccByte] = (UINT8) TempValue; NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RcvEnDly[EccByte]); NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RdDqsDly[EccByte]); NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, EccByte), WrDatDly[EccByte]); } } } } } return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); }