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/* Copyright 2000 AG Electronics Ltd. */
/* This code is distributed without warranty under the GPL v2 (see COPYING) */
#define ASM
#include "ppcreg.h"
#include <ppc_asm.tmpl>
.section ".rom.reset", "ax", @progbits
.globl _start
_start:
b system_reset
.section ".rom.exception_vectors", "ax", @progbits
%%EXCEPTION_VECTOR_TABLE%%
.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits
system_reset:
/*
* Do processor family initialization
*/
%%FAMILY_INIT%%
/*
* Do processor specific initialization
*/
%%PROCESSOR_INIT%%
#if USE_DCACHE_RAM == 1
#define DCACHE_RAM_END (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - 1)
/*
* Initialize data cache blocks
* (assumes cache block size of 32 bytes)
*
* NOTE: This may need to be moved to FAMILY_INIT if
* dcbz is not supported on all CPU's
*/
lis r1, DCACHE_RAM_BASE@h
ori r1, r1, DCACHE_RAM_BASE@l
li r3, (DCACHE_RAM_SIZE / 32)
mtctr r3
0: dcbz r0, r1
addi r1, r1, 32
bdnz 0b
/*
* Set up stack in cache. The SP must be 16-byte (4-word) aligned
* for SYSV EABI or 8-byte (2-word) aligned for PPC EABI, so we make
* it 16-byte aligned to cover both cases. Also we have to ensure that
* the first word is located within the cache.
*/
lis r1, (DCACHE_RAM_BASE+DCACHE_RAM_SIZE)@h
ori r1, r1, (DCACHE_RAM_BASE+DCACHE_RAM_SIZE)@l
lis r0, 0
stwu r0, -4(r1)
stwu r0, -4(r1)
stwu r0, -4(r1)
stwu r0, -4(r1)
#if 0
/*
* Clear stack
*/
lis r4, DCACHE_RAM_BASE@h
ori r4, r4, DCACHE_RAM_BASE@l
lis r7, DCACHE_RAM_END@h
ori r7, r7, DCACHE_RAM_END@l
lis r5, 0
1: stwx r5, 0, r4
addi r4, r4, 4
cmp 0, 0, r4, r7
ble 1b
sync
#endif
/*
* Set up the EABI pointers, before we enter any C code
*/
lis r13, _SDA_BASE_@h
ori r13, r13, _SDA_BASE_@l
lis r2, _SDA2_BASE_@h
ori r2, r2, _SDA2_BASE_@l
/*
* load start address into SRR0 for rfi
*/
lis r3, ppc_main@h
ori r3, r3, ppc_main@l
mtspr SRR0, r3
/*
* load the current MSR into SRR1 so that it will be copied
* back into MSR on rfi
*/
mfmsr r4
mtspr SRR1, r4 // load SRR1 with r4
/*
* If something returns after rfi then die
*/
lis r3, dead@h
ori r3, r3, dead@l
mtlr r3
/*
* Complete rest of initialization in C (ppc_main)
*/
rfi
#endif /* USE_DCACHE_RAM */
/*
* Stop here if something goes wrong
*/
dead:
b dead
/*NOTREACHED*/
/* Remove need for ecrti.o and ectrn.o */
.globl __init
__init:
.globl __fini
__fini:
.globl __CTOR_LIST__
__CTOR_LIST__:
.globl __CTOR_END__
__CTOR_END__:
.globl __DTOR_LIST__
__DTOR_LIST__:
.globl __DTOR_END__
__DTOR_END__:
blr
%%NORTHBRIDGE_INIT%%
|
