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/*
* Memory map:
*
* CONFIG_ROMBASE : start of ROM
* CONFIG_RESET : reset vector (may be at top of ROM)
* _EXCEPTIONS_VECTORS : exception table
*
* CONFIG_ROMSTART : coreboot text
* : payload text
*
* CONFIG_RAMBASE : address to copy payload
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* Re-rewritten by Greg Watson for PPC
*/
/*
* We use ELF as output format. So that we can
* debug the code in some form.
*/
OUTPUT_FORMAT("elf32-powerpc")
ENTRY(_start)
TARGET(binary)
INPUT(coreboot_ram.rom)
SECTIONS
{
/*
* Absolute location of base of ROM
*/
. = CONFIG_ROMBASE;
/*
* Absolute location of reset vector. This may actually be at the
* the top of ROM.
*/
. = CONFIG_RESET;
.reset . : {
*(.rom.reset);
. = ALIGN(16);
}
/*
* Absolute location of exception vector table.
*/
. = CONFIG_EXCEPTION_VECTORS;
.exception_vectors . : {
*(.rom.exception_vectors);
. = ALIGN(16);
}
/*
* Absolute location of coreboot initialization code in ROM.
*/
. = CONFIG_ROMSTART;
.rom . : {
_rom = .;
*(.rom.text);
*(.text);
*(.rom.data);
*(.rodata);
*(EXCLUDE_FILE(coreboot_ram.rom) .data);
. = ALIGN(16);
_erom = .;
}
_lrom = LOADADDR(.rom);
_elrom = LOADADDR(.rom) + SIZEOF(.rom);
/*
* Ram is the coreboot code that runs from RAM.
*/
.ram . : {
_ram = . ;
coreboot_ram.rom(*)
_eram = . ;
}
.sdata : {
_SDA_BASE_ = .;
*(.sdata)
}
.sdata2 : {
_SDA2_BASE_ = .;
*(.sdata2)
}
/*
* Absolute location of where coreboot will be relocated in RAM.
*/
_iseg = CONFIG_RAMBASE;
_eiseg = _iseg + SIZEOF(.ram);
_liseg = _ram;
_eliseg = _eram;
/DISCARD/ : {
*(.comment)
*(.note)
}
}
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