summaryrefslogtreecommitdiff
path: root/src/cpu/intel/socket_PGA370/Kconfig
blob: d3cf7248e600b13ba94bac082228d5eb3c8f5680 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##

config CPU_INTEL_SOCKET_PGA370
	bool
	select CPU_INTEL_MODEL_6XX
	select MMX
	select UDELAY_TSC

if CPU_INTEL_SOCKET_PGA370

# Not all CPUs for Socket 370 can do SSE2
config SSE2
	bool
	default n

config DCACHE_RAM_BASE
	hex
	default 0xcf000

config DCACHE_RAM_SIZE
	hex
	default 0x01000

endif