summaryrefslogtreecommitdiff
path: root/src/drivers/amd/agesa/bootblock.c
blob: 91fcc6b9940e5d88f5d7825f77db5dd967051f2d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
/*
 * This file is part of the coreboot project.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <bootblock_common.h>
#include <halt.h>
#include <timestamp.h>
#include <amdblocks/amd_pci_mmconf.h>
#include <amdblocks/biosram.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic.h>

#define EARLY_VMTRR_FLASH 6

static void set_early_mtrrs(void)
{
	/* Cache the ROM to speed up booting */
	set_var_mtrr(EARLY_VMTRR_FLASH, OPTIMAL_CACHE_ROM_BASE,
		     OPTIMAL_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
}

asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
	enable_pci_mmconf();
	set_early_mtrrs();

	if (CONFIG(UDELAY_LAPIC))
		enable_lapic();

	bootblock_main_with_basetime(base_timestamp);
}

asmlinkage void ap_bootblock_c_entry(void)
{
	enable_pci_mmconf();
	set_early_mtrrs();

	if (CONFIG(UDELAY_LAPIC))
		enable_lapic();

	void (*ap_romstage_entry)(void) = get_ap_entry_ptr();
	ap_romstage_entry(); /* execution does not return */
	halt();
}