blob: 55d39382dbd6fa751c568042621065b050c6935f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
|
#ifndef CPU_X86_CACHE
#define CPU_X86_CACHE
static inline unsigned long read_cr0(void)
{
unsigned long cr0;
asm volatile ("movl %%cr0, %0" : "=r" (cr0));
return cr0;
}
static inline void write_cr0(unsigned long cr0)
{
asm volatile ("movl %0, %%cr0" : : "r" (cr0));
}
static inline void invd(void)
{
asm volatile("invd" ::: "memory");
}
static inline void wbinvd(void)
{
asm volatile ("wbinvd");
}
static inline void enable_cache(void)
{
unsigned long cr0;
cr0 = read_cr0();
cr0 &= 0x9fffffff;
write_cr0(cr0);
}
static inline void disable_cache(void)
{
/* Disable and write back the cache */
unsigned long cr0;
cr0 = read_cr0();
cr0 |= 0x40000000;
wbinvd();
write_cr0(cr0);
wbinvd();
}
#if !defined(__PRE_RAM__)
void x86_enable_cache(void);
#endif
#endif /* CPU_X86_CACHE */
|
