summaryrefslogtreecommitdiff
path: root/src/lib/generic_sdram.c
blob: 7be053748480bb112409958c9cf96f9dd00ef498 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
#include <lib.h> /* Prototypes */

#ifndef RAMINIT_SYSINFO
        #define RAMINIT_SYSINFO 0
#endif

static inline void print_debug_sdram_8(const char *strval, uint32_t val)
{
#if CONFIG_USE_INIT
        printk_debug("%s%02x\r\n", strval, val);
#else
        print_debug(strval); print_debug_hex8(val); print_debug("\r\n");
#endif
}

/* Setup SDRAM */
#if RAMINIT_SYSINFO == 1
void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo)
#else
void sdram_initialize(int controllers, const struct mem_controller *ctrl)
#endif
{
	int i;
	/* Set the registers we can set once to reasonable values */
	for(i = 0; i < controllers; i++) {
		print_debug_sdram_8("Ram1.",i);

	#if RAMINIT_SYSINFO == 1
		sdram_set_registers(ctrl + i , sysinfo);
	#else
		sdram_set_registers(ctrl + i);
	#endif
	}

	/* Now setup those things we can auto detect */
	for(i = 0; i < controllers; i++) {
                print_debug_sdram_8("Ram2.",i);

	#if RAMINIT_SYSINFO == 1
		sdram_set_spd_registers(ctrl + i , sysinfo);
	#else
                sdram_set_spd_registers(ctrl + i);
	#endif

	}

	/* Now that everything is setup enable the SDRAM.
	 * Some chipsets do the work for us while on others 
	 * we need to it by hand.
	 */
	print_debug("Ram3\r\n");

	#if RAMINIT_SYSINFO == 1
	sdram_enable(controllers, ctrl, sysinfo);
	#else
	sdram_enable(controllers, ctrl);
	#endif

	print_debug("Ram4\r\n");
}