1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003 Eric Biederman
* Copyright (C) 2006-2010 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <uart8250.h>
#include <pc80/mc146818rtc.h>
#if CONFIG_USE_OPTION_TABLE
#include "option_table.h"
#endif
/* Should support 8250, 16450, 16550, 16550A type UARTs */
static inline int uart8250_can_tx_byte(unsigned base_port)
{
return inb(base_port + UART_LSR) & UART_MSR_DSR;
}
static inline void uart8250_wait_to_tx_byte(unsigned base_port)
{
while(!uart8250_can_tx_byte(base_port))
;
}
static inline void uart8250_wait_until_sent(unsigned base_port)
{
while(!(inb(base_port + UART_LSR) & UART_LSR_TEMT))
;
}
void uart8250_tx_byte(unsigned base_port, unsigned char data)
{
uart8250_wait_to_tx_byte(base_port);
outb(data, base_port + UART_TBR);
/* Make certain the data clears the fifos */
uart8250_wait_until_sent(base_port);
}
int uart8250_can_rx_byte(unsigned base_port)
{
return inb(base_port + UART_LSR) & UART_LSR_DR;
}
unsigned char uart8250_rx_byte(unsigned base_port)
{
while(!uart8250_can_rx_byte(base_port))
;
return inb(base_port + UART_RBR);
}
void uart8250_init(unsigned base_port, unsigned divisor)
{
/* Disable interrupts */
outb(0x0, base_port + UART_IER);
/* Enable FIFOs */
outb(UART_FCR_FIFO_EN, base_port + UART_FCR);
/* assert DTR and RTS so the other end is happy */
outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR);
/* DLAB on */
outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR);
/* Set Baud Rate Divisor. 12 ==> 115200 Baud */
outb(divisor & 0xFF, base_port + UART_DLL);
outb((divisor >> 8) & 0xFF, base_port + UART_DLM);
/* Set to 3 for 8N1 */
outb(CONFIG_TTYS0_LCS, base_port + UART_LCR);
}
void uart_init(void)
{
/* TODO the divisor calculation is hard coded to standard UARTs. Some
* UARTs won't work with these values. This should be a property of the
* UART used, worst case a Kconfig variable. For now live with hard
* codes as the only devices that might be different are the iWave
* iRainbowG6 and the OXPCIe952 card (and the latter is memory mapped)
*/
unsigned int div = (115200 / CONFIG_TTYS0_BAUD);
#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE
static const unsigned char divisor[8] = { 1, 2, 3, 6, 12, 24, 48, 96 };
unsigned b_index = 0;
#if defined(__PRE_RAM__)
b_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
b_index &= 7;
div = divisor[ttys0_index];
#else
if (get_option(&b_index, "baud_rate") == 0) {
div = divisor[b_index];
}
#endif
#endif
uart8250_init(CONFIG_TTYS0_BASE, div);
}
|
