path: root/src/mainboard/amd/pistachio/Config.lb

##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##
##
##


##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
	default ROM_SECTION_SIZE   = FALLBACK_SIZE
	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
	default ROM_SECTION_OFFSET = 0
end

##
## Compute the start location and size size of
## The coreboot bootloader.
##
default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)

##
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )

##
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o

#dir /drivers/si/3114

if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE
	object get_bus_conf.o
	object irq_tables.o
end

if HAVE_ACPI_TABLES
	object acpi_tables.o
	object fadt.o
	makerule dsdt.c
		depends "$(MAINBOARD)/acpi/*.asl"
		action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/acpi/dsdt.asl"
		action  "mv dsdt.hex dsdt.c"
	end
	object ./dsdt.o
end

#object reset.o

if USE_DCACHE_RAM

	if CONFIG_USE_INIT

		makerule ./cache_as_ram_auto.o
			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
		end

	else

		makerule ./cache_as_ram_auto.inc
			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
		end

	end

end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
if USE_DCACHE_RAM
	if CONFIG_USE_INIT
		ldscript /cpu/x86/32bit/entry32.lds
	end

	if CONFIG_USE_INIT
		ldscript      /cpu/amd/car/cache_as_ram.lds
	end
end

##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
	mainboardinit cpu/x86/16bit/reset16.inc
	ldscript /cpu/x86/16bit/reset16.lds
else
	mainboardinit cpu/x86/32bit/reset32.inc
	ldscript /cpu/x86/32bit/reset32.lds
end

##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds

if USE_DCACHE_RAM
	##
	## Setup Cache-As-Ram
	##
	mainboardinit cpu/amd/car/cache_as_ram.inc
end

###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
	if USE_DCACHE_RAM
		ldscript /arch/i386/lib/failover.lds
	else
		ldscript /arch/i386/lib/failover.lds
		mainboardinit ./failover.inc
	end
end

###
### O.k. We aren't just an intermediary anymore!
###

##
## Setup RAM
##
if USE_DCACHE_RAM

	if CONFIG_USE_INIT
		initobject cache_as_ram_auto.o
	else
		mainboardinit ./cache_as_ram_auto.inc
	end

end

##
## Include the secondary Configuration files
##
config chip.h

#The variables belong to mainboard are defined here.

#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
#Define vga_rom_address = 0xfff0000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
#					   1: the system allows a PCIE link to be established on Dev2 or Dev3.
#Define gfx_dual_slot, 0: single slot, 1: dual slot
#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
#Define gfx_tmds, 0: didn't support TMDS, 1: support
#Define gfx_compliance, 0: didn't support compliance, 1: support
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
chip northbridge/amd/amdk8/root_complex
	device apic_cluster 0 on
		chip cpu/amd/socket_AM2
		device apic 0 on end
		end
	end
	device pci_domain 0 on
		chip northbridge/amd/amdk8
			device pci 18.0 on #  southbridge, K8 HT Configuration
				chip southbridge/amd/rs690
					device pci 0.0 on end # HT  	0x7910
				#	device pci 0.1 off end # CLK
					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
						chip drivers/pci/onboard
							device pci 5.0 on end	# Internal Graphics 0x791F
							register "rom_address" = "0xfff00000"
						end
					end
					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
					device pci 3.0 off end # PCIE P2P bridge	0x791b
					device pci 4.0 on end # PCIE P2P bridge 0x7914
					device pci 5.0 on end # PCIE P2P bridge 0x7915
					device pci 6.0 on end # PCIE P2P bridge 0x7916
					device pci 7.0 on end # PCIE P2P bridge 0x7917
					device pci 8.0 off end # NB/SB Link P2P bridge
					register "vga_rom_address" = "0xfff00000"
					register "gpp_configuration" = "4"
					register "port_enable" = "0xfc"
					register "gfx_dev2_dev3" = "1"
					register "gfx_dual_slot" = "0"
					register "gfx_lane_reversal" = "0"
					register "gfx_tmds" = "0"
					register "gfx_compliance" = "0"
					register "gfx_reconfiguration" = "1"
					register "gfx_link_width" = "0"
				end
				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
					device pci 12.0 on end # SATA  0x4380
					device pci 13.0 on end # USB   0x4387
					device pci 13.1 on end # USB   0x4388
					device pci 13.2 on end # USB   0x4389
					device pci 13.3 on end # USB   0x438a
					device pci 13.4 on end # USB   0x438b
					device pci 13.5 on end # USB 2 0x4386
	 				device pci 14.0 on # SM        0x4385
						chip drivers/generic/generic #dimm 0-0-0
							device i2c 50 on end
						end
						chip drivers/generic/generic #dimm 0-0-1
							device i2c 51 off end
						end
						chip drivers/generic/generic #dimm 0-1-0
							device i2c 52 off end
						end
						chip drivers/generic/generic #dimm 0-1-1
							device i2c 53 off end
						end
					end # SM
				device pci 14.1 on end # IDE    0x438c
				device pci 14.2 on end # HDA    0x4383
				device pci 14.3 on end # LPC	0x438d
				device pci 14.4 on end # PCI 0x4384
				device pci 14.5 on end # ACI 0x4382
				device pci 14.6 on end # MCI 0x438e
					register "ide0_enable" = "1"
					register "sata0_enable" = "1"
					register "hda_viddid" = "0x10ec0882"
				end	#southbridge/amd/sb600
			end #  device pci 18.0

			device pci 18.1 on end		# K8 Address Map
			device pci 18.2 on end		# K8 DRAM Controller and HT Trace Mode
			device pci 18.3 on end		# K8 Miscellaneous Control
		end		#northbridge/amd/amdk8
	end #pci_domain
end		#northbridge/amd/amdk8/root_complex