summaryrefslogtreecommitdiff
path: root/src/mainboard/amd/solo/Config.lb
blob: 107e6ad4aa7be801435968c504f768e98a346a51 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
#
###
### Build code to export a CMOS option table
###
default HAVE_OPTION_TABLE=1
option HAVE_MP_TABLE=0
####
#### Build options
####
#
###
### Location of the DIMM EEPROMS on the SMBUS
### This is fixed into a narrow range by the DIMM package standard.
###
option SMBUS_MEM_DEVICE_START=(0xa << 3)
option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +1)
option SMBUS_MEM_DEVICE_INC=1
default CONFIG_CONSOLE_VGA=0
default CONFIG_CONSOLE_LOGBUF=0
default CONFIG_CONSOLE_SROM=0
default CONFIG_SMP=0
default CONFIG_UDELAY_TSC=0
#
###
### Customize our winbond superio chip for this motherboard
###
option SIO_BASE=0x2e
option SIO_SYSTEM_CLK_INPUT=0
option CONFIG_CONSOLE_SERIAL8250=0
#
###
### Build code for the fallback boot
###
option HAVE_FALLBACK_BOOT=1
#
###
### Build code to reset the motherboard from linuxBIOS
###
## option HAVE_HARD_RESET=1
#
###
### Build code to export a programmable irq routing table
###
option HAVE_PIRQ_TABLE=1
option IRQ_SLOT_COUNT=7
#
###
### Build code to export an x86 MP table
### Useful for specifying IRQ routing values
###
##option HAVE_MP_TABLE=1
#
###
### Do not build special code for the keyboard
###
default NO_KEYBOARD=1
#
###
### Build code for SMP support
### Only worry about 2 micro processors
###
##option CONFIG_SMP=1
option MAX_CPUS=1
#
###
### Build code to setup a generic IOAPIC
###
option CONFIG_IOAPIC=1
#
###
### MEMORY_HOLE instructs earlymtrr.inc to
### enable caching from 0-640KB and to disable 
### caching from 640KB-1MB using fixed MTRRs 
###
### Enabling this option breaks SMP because secondary
### CPU identification depends on only variable MTRRs
### being enabled.
###
option MEMORY_HOLE=0
#
###
### Enable both fixed and variable MTRRS
### When we setup MTRRs in mtrr.c  
###
### We must setup the fixed mtrrs or we confuse SMP secondary
### processor identification
###
option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
#
###
### Clean up the motherboard id strings
###
option MAINBOARD_PART_NUMBER="Solo7"
option MAINBOARD_VENDOR="AMD"
#
###
### Let Assembly code know where on the pci bus the AMD southbridge is
###
option AMD8111_DEV=0x3800
#
###
### Call the final_mainboard_fixup function
###
option FINAL_MAINBOARD_FIXUP=1
#
###
### Figure out which type of linuxBIOS image to build
### If we aren't a fallback image we must be a normal image
### This is useful for optional includes
###
default USE_FALLBACK_IMAGE=0
option USE_NORMAL_IMAGE=(! USE_FALLBACK_IMAGE)
#
####
#### LinuxBIOS layout values
####
#
### ROM_SIZE is the size of boot ROM that this board will use.
option ROM_SIZE=262144
#
### ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
option ROM_IMAGE_SIZE=65535
#
###
### Use a small 8K stack
###
option STACK_SIZE=0x2000
#
###
### Use a small 8K heap
###
option HEAP_SIZE=0x2000
#
###
### Only use the option table in a normal image
###
option USE_OPTION_TABLE=!USE_FALLBACK_IMAGE
#
###
### Compute the location and size of where this firmware image
### (linuxBIOS plus bootloader) will live in the boot rom chip.
###
default FALLBACK_SIZE=65536
if USE_FALLBACK_IMAGE 
  option ROM_SECTION_SIZE  = FALLBACK_SIZE
  option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
end
if USE_NORMAL_IMAGE
  option ROM_SECTION_SIZE  = (ROM_SIZE - FALLBACK_SIZE)
  option ROM_SECTION_OFFSET= 0
end
#
###
### Compute the start location and size size of
### The linuxBIOS bootloader.
###
option PAYLOAD_SIZE            = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
option CONFIG_ROM_STREAM     = 1
#
###
### Compute where this copy of linuxBIOS will start in the boot rom
###
option _ROMBASE      = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
#
###
### Compute a range of ROM that can cached to speed up linuxBIOS,
### execution speed.
###
##expr XIP_ROM_SIZE = 65536
##expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE
##option XIP_ROM_SIZE=65536
##option XIP_ROM_BASE=0xffff0000
#
## XIP_ROM_SIZE && XIP_ROM_BASE values that work.
##option XIP_ROM_SIZE=0x8000
##option XIP_ROM_BASE=0xffff8000
#
###
### Compute where the SMP startup code needs to live
### FIXME I don't see how to make this work for the normal image....
###
option START_CPU_SEG=0xf0000
#
#
###
### Set all of the defaults for an x86 architecture
###
#
#
###
### Build the objects we have code for in this directory.
###
##object mainboard.o
driver mainboard.o
object static_devices.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#
arch i386 end
cpu k8 end
#
option DEBUG=1
default USE_FALLBACK_IMAGE=1
option A=(1+2)
option B=0xa
#
###
### Build our 16 bit and 32 bit linuxBIOS entry code
###
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
#
###
### Build our reset vector (This is where linuxBIOS is entered)
###
if USE_FALLBACK_IMAGE 
  mainboardinit cpu/i386/reset16.inc 
  ldscript /cpu/i386/reset16.lds 
end

if USE_NORMAL_IMAGE
  mainboardinit cpu/i386/reset32.inc 
  ldscript /cpu/i386/reset32.lds 
end
#
#### Should this be in the northbridge code?
#mainboardinit archi386/lib/cpu_reset.inc
#
###
### Include an id string (For safe flashing)
###
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
#
####
#### This is the early phase of linuxBIOS startup 
#### Things are delicate and we test to see if we should
#### failover to another image.
####
option MAX_REBOOT_CNT=2
##ldscript arch/i386/lib/failover.lds USE_FALLBACK_IMAGE
#
###
### Setup our mtrrs
###
mainboardinit cpu/k8/earlymtrr.inc
#
#
###
### Only the bootstrap cpu makes it here.
### Failover if we need to 
###
#
if USE_FALLBACK_IMAGE
  mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc 
end
#
####
#### O.k. We aren't just an intermediary anymore!
####
#
###
### When debugging disable the watchdog timer
###
##option MAXIMUM_CONSOLE_LOGLEVEL=7
#default MAXIMUM_CONSOLE_LOGLEVEL=7
#option DISABLE_WATCHDOG= (MAXIMUM_CONSOLE_LOGLEVEL >= 8) 
#if DISABLE_WATCHDOG
#  mainboardinit southbridgeamd/amd8111/disable_watchdog.inc 
#end
#
###
### Setup the serial port
###
#mainboardinit superiowinbond/w83627hf/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
if USE_FALLBACK_IMAGE mainboardinit archi386/lib/noop_failover.inc  end
#
###
### Romcc output
###
#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
#mainboardinit .failover.inc
makerule ./auto.E dep "$(MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
mainboardinit ./auto.inc
#
###
### Setup RAM
###
mainboardinit ram/ramtest.inc
mainboardinit southbridge/amd/amd8111/smbus.inc
mainboardinit sdram/generic_dump_spd.inc
#
###
### Include the secondary Configuration files 
###
northbridge amd/amdk8
end
southbridge amd/amd8111
end
#mainboardinit archi386/smp/secondary.inc
superio NSC/pc87360
	register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1"
end
dir /pc80
##dir /src/superio/winbond/w83627hf
cpu p5 end
cpu p6 end
cpu k7 end
cpu k8 end