blob: dfaa97d15ba270389d797d303c11088ac2a02ccd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
|
#*****************************************************************************
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
# Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#*****************************************************************************
entries
#start-bit length config config-ID name
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 r 0 reboot_counter
#392 3 r 0 unused
#400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
420 4 e 7 boot_second
424 4 e 7 boot_third
428 4 r 0 boot_index
432 8 r 0 boot_countdown
440 8 e 10 sata_mode
448 8 e 11 sata_speed
#728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
enumerations
#ID value text
#1 0 Disable
#1 1 Enable
4 0 Fallback
4 1 Normal
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Network
7 1 HDD
7 2 Floppy
7 8 Fallback_Network
7 9 Fallback_HDD
7 10 Fallback_Floppy
10 0 IDE
10 2 AHCI
11 1 3Gbps
11 0 6Gbps
checksums
checksum 392 455 984
|
