1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
|
#define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/nsc/pc87417/pc87417_early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x71
unsigned device=(ctrl->channel0[0])>>8;
smbus_send_byte(SMBUS_HUB, device);
}
#if 0
static inline void change_i2c_mux(unsigned device)
{
#define SMBUS_HUB 0x71
int ret;
print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
ret = smbus_send_byte(SMBUS_HUB, device);
print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
}
#endif
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
/* tyan does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#define RC0 (6<<8)
#define RC1 (7<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "northbridge/amd/amdk8/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
RC0|DIMM0, RC0|DIMM2, 0, 0,
RC0|DIMM1, RC0|DIMM3, 0, 0,
RC1|DIMM0, RC1|DIMM2, 0, 0,
RC1|DIMM1, RC1|DIMM3, 0, 0,
};
int needs_reset;
unsigned bsp_apicid = 0;
struct mem_controller ctrl[8];
unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc();
//enable RTC
pc87417_enable_dev(RTC_DEV);
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx);
}
// post_code(0x32);
pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
// post_code(0x33);
uart_init();
// post_code(0x34);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
setup_blast_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
wait_all_core0_started();
start_other_cores();
#endif
wait_all_aps_started(bsp_apicid);
needs_reset |= ht_setup_chains_x();
bcm5785_early_setup();
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
nodes = get_nodes();
//It's the time to set ctrl now;
fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
#if 0
int i;
for(i=4;i<8;i++) {
change_i2c_mux(i);
dump_smbus_registers();
}
#endif
memreset_setup();
// init_timer();
sdram_initialize(nodes, ctrl);
#if 0
print_pci_devices();
#endif
#if 0
dump_pci_devices();
#endif
post_cache_as_ram();
}
|