1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <ec/dell/mec5055/mec5055.h>
#include <superio/smsc/ece5048/ece5048.h>
void mainboard_pch_lpc_setup(void)
{
/* port 0x910 and 0x911 is needed to initialize the EC */
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x007c0901);
}
void mainboard_late_rcba_config(void)
{
RCBA32(BUC) = 0x00000010;
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 0 },
{ 1, 1, 0 },
{ 1, 0, 1 },
{ 1, 2, 1 },
{ 1, 0, 2 },
{ 1, 0, 2 },
{ 1, 0, 3 },
{ 1, 1, 3 },
{ 1, 2, 4 },
{ 1, 1, 4 },
{ 1, 1, 5 },
{ 1, 1, 5 },
{ 1, 2, 6 },
{ 1, 0, 6 },
};
void mainboard_early_init(int s3resume)
{
ece5048_early_init(0x94e);
mec5055_early_init();
}
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
read_spd(&spd[0], 0x50, id_only);
read_spd(&spd[2], 0x52, id_only);
}
|
