summaryrefslogtreecommitdiff
path: root/src/mainboard/eaglelion/5bcm/Config.lb
blob: d1f02be8c5f6f1353ddd177466df9bc561f4f901 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb

##
## Set all of the defaults for an x86 architecture
##

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o

if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o

##
## Romcc output
##
makerule ./failover.E
	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end

makerule ./failover.inc
	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end

makerule ./auto.E 
	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc 
	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end

##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds

##
## Build our reset vector (This is where coreboot is entered)
##
if CONFIG_USE_FALLBACK_IMAGE 
	mainboardinit cpu/x86/16bit/reset16.inc 
	ldscript /cpu/x86/16bit/reset16.lds 
else
	mainboardinit cpu/x86/32bit/reset32.inc 
	ldscript /cpu/x86/32bit/reset32.lds 
end

### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc

##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds

###
### This is the early phase of coreboot startup 
### Things are delicate and we test to see if we should
### failover to another image.
###
if CONFIG_USE_FALLBACK_IMAGE
	ldscript /arch/i386/lib/failover.lds 
	mainboardinit ./failover.inc
end

###
### O.k. We aren't just an intermediary anymore!
###

##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/amd/model_gx1/cpu_setup.inc
mainboardinit cpu/amd/model_gx1/gx_setup.inc
mainboardinit ./auto.inc

##
## Include the secondary Configuration files 
##
dir /pc80
config chip.h

chip northbridge/amd/gx1
  device pci_domain 0 on 
    device pci 0.0 on end
      chip southbridge/amd/cs5530
        device pci 12.0 on
          chip superio/nsc/pc97317
            device pnp 2e.0 on		# Keyboard
               io 0x60 = 0x60
               io 0x62 = 0x64
              irq 0x70 = 1
            end
            device pnp 2e.1 on		# Mouse
              irq 0x70 = 12
            end
            device pnp 2e.2 on		# RTC
               io 0x60 = 0x70
              irq 0x70 = 8
            end
            device pnp 2e.3 off		# FDC
            end
            device pnp 2e.4 on		# Parallel Port
               io 0x60 = 0x378
              irq 0x70 = 7
            end
            device pnp 2e.5 on		# COM2
               io 0x60 = 0x2f8
              irq 0x70 = 3
            end
            device pnp 2e.6 on		# COM1
               io 0x60 = 0x3f8
              irq 0x70 = 4
            end
            device pnp 2e.7 on		# GPIO
               io 0x60 = 0xe0
            end
            device pnp 2e.8 on		# Power Management
               io 0x60 = 0xe800
            end
            register "com1" = "{115200}"
            register "com2" = "{38400}"
          end
        device pci 12.1 off end		# SMI
        device pci 12.2 on  end		# IDE
        device pci 12.3 off end 	# Audio
        device pci 12.4 off end		# VGA
      end
    end
  end

  chip cpu/amd/model_gx1
  end

end