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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
/* Save the BIST result. */
movl %eax, %ebp
cache_as_ram:
post_code(0x20)
/*
* Nothing to do here on qemu, RAM works just fine without any
* initialization.
*/
post_code(0x21)
/*
* Set up the stack pointer, use top of real mode (640k) memory.
* This value also keeps the copy_and_run stack out of the way
* of big ramstages. The ramstage will load its own %esp so
* there is no harm in using this value.
*/
movl $0xa0000, %eax
movl %eax, %esp
/* Restore the BIST result. */
movl %ebp, %eax
movl %esp, %ebp
pushl %eax
before_romstage:
post_code(0x29)
/* Call romstage.c main function. */
call romstage_main
post_code(0x30)
__main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
call copy_and_run
.Lhlt:
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
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