summaryrefslogtreecommitdiff
path: root/src/mainboard/facebook/monolith/devicetree.cb
blob: 974d00e41a40b48d89f24b0e07dd53083388d335 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
chip soc/intel/skylake

	register "deep_s5_enable_ac" = "0"
	register "deep_s5_enable_dc" = "0"
	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	register "gpe0_dw0" = "GPP_C"
	register "gpe0_dw1" = "GPP_D"
	register "gpe0_dw2" = "GPP_E"

	# Set the fixed lpc ranges
	# enable COMA at 3f8 and COMB at 3e8 (instead of the default 2f8)
	# enable the embedded controller
	register "lpc_iod" = "0x0070"
	register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66"

	# CPLD host command ranges are in 0x280-0x2BF
	# EC PNP registers are at 0x6e and 0x6f
	register "gen1_dec" = "0x003c0281"
	register "gen3_dec" = "0x0004006d"

	# LPC serial IRQ
	register "serirq_mode" = "SERIRQ_CONTINUOUS"

	# "Intel SpeedStep Technology"
	register "eist_enable" = "1"

	# DPTF
	register "dptf_enable" = "1"

	# FSP Configuration
	register "ScsEmmcHs400Enabled" = "1"
	register "SkipExtGfxScan" = "1"
	register "SaGv" = "SaGv_Enabled"
	register "HeciEnabled" = "0"

	register "SataSalpSupport" = "1"
	register "SataPortsEnable" = "{ \
		[0]	= 1, \
		[1]	= 0, \
		[2]	= 0, \
		[3]	= 0, \
		[4]	= 0, \
		[5]	= 0, \
		[6]	= 0, \
		[7]	= 0, \
	}"

	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
	register "PmConfigSlpS3MinAssert" = "2"

	# SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
	register "PmConfigSlpS4MinAssert" = "4"

	# SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
	register "PmConfigSlpSusMinAssert" = "3"

	# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
	register "PmConfigSlpAMinAssert" = "3"

	# VR Settings Configuration for 4 Domains
	#+----------------+-------+-------+-------+-------+
	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
	#+----------------+-------+-------+-------+-------+
	#| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
	#| Psi2Threshold  | 5A    | 5A    | 5A    | 5A    |
	#| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
	#| Psi3Enable     | 1     | 1     | 1     | 1     |
	#| Psi4Enable     | 1     | 1     | 1     | 1     |
	#| ImonSlope      | 0     | 0     | 0     | 0     |
	#| ImonOffset     | 0     | 0     | 0     | 0     |
	#| IccMax         | 5.1A  | 32A   | 35A   | 31A   |
	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
	#+----------------+-------+-------+-------+-------+
	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
		.vr_config_enable = 1, \
		.psi1threshold = VR_CFG_AMP(20), \
		.psi2threshold = VR_CFG_AMP(5), \
		.psi3threshold = VR_CFG_AMP(1), \
		.psi3enable = 1, \
		.psi4enable = 1, \
		.imon_slope = 0, \
		.imon_offset = 0, \
		.icc_max = VR_CFG_AMP(5.1), \
		.voltage_limit = 1520 \
	}"

	register "domain_vr_config[VR_IA_CORE]" = "{
		.vr_config_enable = 1, \
		.psi1threshold = VR_CFG_AMP(20), \
		.psi2threshold = VR_CFG_AMP(5), \
		.psi3threshold = VR_CFG_AMP(1), \
		.psi3enable = 1, \
		.psi4enable = 1, \
		.imon_slope = 0, \
		.imon_offset = 0, \
		.icc_max = VR_CFG_AMP(32), \
		.voltage_limit = 1520 \
	}"

	register "domain_vr_config[VR_GT_UNSLICED]" = "{
		.vr_config_enable = 1, \
		.psi1threshold = VR_CFG_AMP(20), \
		.psi2threshold = VR_CFG_AMP(5), \
		.psi3threshold = VR_CFG_AMP(1), \
		.psi3enable = 1, \
		.psi4enable = 1, \
		.imon_slope = 0, \
		.imon_offset = 0, \
		.icc_max = VR_CFG_AMP(35),\
		.voltage_limit = 1520 \
	}"

	register "domain_vr_config[VR_GT_SLICED]" = "{
		.vr_config_enable = 1, \
		.psi1threshold = VR_CFG_AMP(20), \
		.psi2threshold = VR_CFG_AMP(5), \
		.psi3threshold = VR_CFG_AMP(1), \
		.psi3enable = 1, \
		.psi4enable = 1, \
		.imon_slope = 0, \
		.imon_offset = 0, \
		.icc_max = VR_CFG_AMP(31), \
		.voltage_limit = 1520 \
	}"

	# Send an extra VR mailbox command for the PS4 exit issue
	register "SendVrMbxCmd" = "2"

	# Enable Root ports.
	# PCIE Port 1 disabled
	# PCIE Port 2 disabled

	# PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard
	register "PcieRpEnable[2]" = "1"
	# Disable CLKREQ#
	register "PcieRpClkReqSupport[2]" = "0"
	# Set MaxPayload to 256 bytes
	register "PcieRpMaxPayload[2]" = "RpMaxPayload_256"
	# Enable Latency Tolerance Reporting Mechanism
	register "PcieRpLtrEnable[2]" = "1"
	# Enable Advanced Error Reporting
	register "PcieRpAdvancedErrorReporting[2]" = "1"
	# Disable Aspm
	register "pcie_rp_aspm[2]" = "AspmDisabled"

	# PCIE Port 4 disabled
	# PCIE Port 5 x1 -> MODULE i219

	# PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard
	register "PcieRpEnable[5]" = "1"
	register "PcieRpClkReqSupport[5]" = "0"
	# Set MaxPayload to 256 bytes
	register "PcieRpMaxPayload[5]" = "RpMaxPayload_256"
	# Enable Latency Tolerance Reporting Mechanism
	register "PcieRpLtrEnable[5]" = "1"
	# Enable Advanced Error Reporting
	register "PcieRpAdvancedErrorReporting[5]" = "1"
	# Disable Aspm
	register "pcie_rp_aspm[5]" = "AspmDisabled"

	# PCIE Port 7 Disabled
	# PCIE Port 8 Disabled

	# PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA
	register "PcieRpEnable[8]" = "1"
	# Disable CLKREQ#
	register "PcieRpClkReqSupport[8]" = "0"
	# Use Hot Plug subsystem
	register "PcieRpHotPlug[8]" = "1"
	# Set MaxPayload to 256 bytes
	register "PcieRpMaxPayload[8]" = "RpMaxPayload_256"
	# Enable Latency Tolerance Reporting Mechanism
	register "PcieRpLtrEnable[8]" = "1"
	# Enable Advanced Error Reporting
	register "PcieRpAdvancedErrorReporting[8]" = "1"
	# Disable Aspm
	register "pcie_rp_aspm[8]" = "AspmDisabled"

	# USB 2.0 Enable all ports
	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB-C Port 2
	register "usb2_ports[1]" = "USB2_PORT_MID(OC1)"		# USB3_TYPE-A Port 1
	register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"		# USB3_TYPE-A Port 2
	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB-C Port 1
	register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)"	# M2 Port
	register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)"	# Audio board

	# USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB-C Port 2
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3_TYPE-A Port 1
	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3_TYPE-A Port 2
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB-C Port 1

	register "SsicPortEnable" = "0"

	# Must leave UART0 enabled or SD/eMMC will not work as PCI
	register "SerialIoDevMode" = "{ \
		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled, \
		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled, \
		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled, \
		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled, \
		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled, \
		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled, \
		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled, \
		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
		[PchSerialIoIndexUart0] = PchSerialIoPci, \
		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
		[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
	}"

	# Lock Down
	register "common_soc_config" = "{
		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
	}"

	device cpu_cluster 0 on
		device lapic 0 on end
	end
	device domain 0 on
		device pci 00.0 on  end # Host Bridge
		device pci 02.0 on  end # Integrated Graphics Device
		device pci 04.0 on  end # Thermal Subsystem
		device pci 05.0 off end # SA IMGU
		device pci 08.0 on  end # Gaussian Mixture Model
		device pci 14.0 on  end # USB xHCI
		device pci 14.1 on  end # USB xDCI (OTG)
		device pci 14.2 on  end # Thermal Subsystem
		device pci 14.3 off end # Camera
		device pci 17.0 on  end # SATA
		device pci 1c.2 on  end # PCI Express Port 3 x1 baseboard WWAN
		device pci 1c.5 on  end # PCI Express Port 6 x1 baseboard i210
		device pci 1d.0 on  end # PCI Express Port 9 x4 FPGA
		device pci 1e.0 on  end # UART #0
		device pci 1e.4 on  end # eMMC
		device pci 1f.0 on  # LPC Interface
			chip drivers/pc80/tpm
				device pnp 0c31.0 on end
			end
		end # LPC Bridge
		device pci 1f.1 on  end # P2SB
		device pci 1f.2 on  end # Power Management Controller
		device pci 1f.3 on  end # HDA Controller for HDMI only
		device pci 1f.4 on  end # SMBus
		device pci 1f.5 on  end # PCH SPI
		device pci 1f.6 on  end # GbE
	end
end