summaryrefslogtreecommitdiff
path: root/src/mainboard/foxconn/d41s/devicetree.cb
blob: 0fd9e29cc97dd5978b5dfd6a0d91fd12321b9f06 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
#
# This file is part of the coreboot project.
#
# Copyright (C) 2015  Damien Zammit <damien@zamaudio.com>
# Copyright (C) 2018  Arthur Heymans <arthur@aheymans.xyz>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#

chip northbridge/intel/pineview		# Northbridge
  register "gfx.use_spread_spectrum_clock" = "0"
  register "use_crt" = "1"
  register "use_lvds" = "0"

  device cpu_cluster 0 on		# APIC cluster
    chip cpu/intel/socket_FCBGA559	# CPU
      device lapic 0 on end		# APIC
    end
  end
  device domain 0 on			# PCI domain
    device pci 0.0 on end		# Host Bridge
    device pci 1.0 off end		# PEG
    device pci 2.0 on end		# Integrated graphics controller
    device pci 2.1 off end		# Integrated graphics controller 2
    chip southbridge/intel/i82801gx	# Southbridge
      register "pirqa_routing" = "0x0b"
      register "pirqb_routing" = "0x0b"
      register "pirqc_routing" = "0x0b"
      register "pirqd_routing" = "0x0b"
      register "pirqe_routing" = "0x0b"
      register "pirqf_routing" = "0x0b"
      register "pirqg_routing" = "0x0b"
      register "pirqh_routing" = "0x0b"
      register "sata_ahci" = "0x1"
      register "sata_ports_implemented" = "0x3"
      register "gpe0_en" = "0x441"

      device pci 1b.0 on end		# Audio
      device pci 1c.0 on end		# PCIe 1
      device pci 1c.1 on end		# PCIe 2 (NIC)
      device pci 1c.2 off end		# PCIe 3
      device pci 1c.3 off end		# PCIe 4
      # (PCIe 5 and 6 not on nm10?)
      device pci 1d.0 on end		# USB
      device pci 1d.1 on end		# USB
      device pci 1d.2 on end		# USB
      device pci 1d.3 on end		# USB
      device pci 1d.7 on end		# USB
      device pci 1e.0 on end		# PCI bridge
      #device pci 1e.2 off end		# AC'97 Audio (not on nm10?)
      #device pci 1e.3 off end		# AC'97 Modem (not on nm10?)
      device pci 1f.0 on		# ISA bridge
        chip superio/ite/it8721f	# Super I/O
          device pnp 2e.0 off end	# Floppy
          device pnp 2e.1 on		# COM1
            io 0x60 = 0x3f8
            irq 0x70 = 4
          end
          device pnp 2e.2 on		# COM2
            io 0x60 = 0x2f8
            irq 0x70 = 3
          end
          device pnp 2e.3 on		 # PP
            io 0x60 = 0x378
            io 0x62 = 0
            irq 0x70 = 7
          end
          device pnp 2e.4 on		# EC
            io 0x60 = 0xa10
            io 0x62 = 0xa00
            irq 0x70 = 0
          end
          device pnp 2e.5 on		# PS/2 keyboard / mouse
            io 0x60 = 0x60
            io 0x62 = 0x64
            irq 0x70 = 1		# PS/2 keyboard interrupt
          end
          device pnp 2e.6 on		# PS/2 mouse
            irq 0x70 = 12
          end
          device pnp 2e.7 off end	# GPIO
          device pnp 2e.a on		# CIR
            io 0x60 = 0x3e0
            irq 0x70 = 10
          end
        end
      end
      device pci 1f.1 off end		# PATA
      device pci 1f.2 on end		# SATA
      device pci 1f.3 on				# SMbus
        chip drivers/i2c/ck505
          register "mask" = "{ 0x00, 0x80, 0xff, 0xff,
                               0xff }"
          register "regs" = "{ 0x00, 0x80, 0xfe, 0xff,
                               0xfc }"
          device i2c 69 on end
        end
      end
    end
  end
end