summaryrefslogtreecommitdiff
path: root/src/mainboard/gigabyte/m57sli/get_bus_conf.c
blob: 70769602981c50cf23c1348390123b0f062b8f51 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
/*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2007 AMD
 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
#if CONFIG_LOGICAL_CPUS==1
#include <cpu/amd/dualcore.h>
#endif

#include <cpu/amd/amdk8_sysconf.h>
#include <stdlib.h>


// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
        unsigned char bus_isa;
        unsigned char bus_mcp55[8]; //1
        unsigned apicid_mcp55;


unsigned pci1234x[] = 
{        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
        0x0000ff0,
//        0x0000ff0,
//        0x0000ff0,
//        0x0000ff0,
//        0x0000ff0,
//        0x0000ff0,
//        0x0000ff0,
//        0x0000ff0
};
unsigned hcdnx[] = 
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
	0x20202020,
//	0x20202020,
//        0x20202020,
//        0x20202020,
//        0x20202020,
//        0x20202020,
//        0x20202020,
//        0x20202020,
};
unsigned bus_type[256]; 

extern void get_sblk_pci1234(void);

static unsigned get_bus_conf_done = 0;

void get_bus_conf(void)
{

	unsigned apicid_base;
	unsigned sbdn;

        device_t dev;
        int i, j;

        if(get_bus_conf_done==1) return; //do it only once

        get_bus_conf_done = 1;

        sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
        for(i=0;i<sysconf.hc_possible_num; i++) {
                sysconf.pci1234[i] = pci1234x[i];
                sysconf.hcdn[i] = hcdnx[i];
        }

        get_sblk_pci1234();

	sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
	sbdn = sysconf.sbdn;

	for(i=0; i<8; i++) {
		bus_mcp55[i] = 0;
	}
	
	for(i=0;i<256; i++) {
		bus_type[i] = 0;
	}

	bus_type[0] = 1; //pci
	
	bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;

	bus_type[bus_mcp55[0]] = 1;

                /* MCP55 */
                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06,0));
                if (dev) {
                        bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
                        bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
                        bus_mcp55[2]++;
			for(j=bus_mcp55[1];j<bus_mcp55[2]; j++) bus_type[j] = 1;
                }
                else {
                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);

                        bus_mcp55[1] = 2;
                        bus_mcp55[2] = 3;
                }

		for(i=2; i<8;i++) {
	                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0));
        	        if (dev) {
                	        bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
	                        bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
        	                bus_isa++;
				for(j=bus_mcp55[i];j<bus_isa; j++) bus_type[j] = 1;
	                }
        	        else {
                	        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
	                        bus_isa = bus_mcp55[i-1]+1;
        	        }
		}


/*I/O APICs:	APIC ID	Version	State		Address*/
#if CONFIG_LOGICAL_CPUS==1
	apicid_base = get_apicid_base(1);
#else 
	apicid_base = CONFIG_MAX_PHYSICAL_CPUS; 
#endif
	apicid_mcp55 = apicid_base+0;

}