blob: 1698c881f1b01bec2a39342c1f5c6830b3578e9d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
#include <variant/ec.h>
#include <variant/gpio.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 /* OEM revision */
)
{
#include <soc/intel/common/block/acpi/acpi/platform.asl>
/* global NVS and variables */
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/jasperlake/acpi/southbridge.asl>
}
/* Mainboard hooks */
#include "acpi/mainboard.asl"
}
#if CONFIG(VARIANT_HAS_CAMERA_ACPI)
/* Camera */
#include <variant/acpi/camera.asl>
#endif
/* Include Low power idle table for a short term workaround to enable
S0ix. Once cr50 pulse width is fixed, this can be removed. */
#include <soc/intel/common/acpi/lpit.asl>
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
#include <ec/google/chromeec/acpi/superio.asl>
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
}
}
|
