blob: ece1201c9c638cfe3040eb9f8c7e4d2d33d42704 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/acpimmio.h>
#include <bootblock_common.h>
#include <baseboard/variants.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <delay.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <soc/pci_devs.h>
void bootblock_mainboard_early_init(void)
{
size_t num_gpios;
uint32_t dword;
const struct soc_amd_gpio *gpios;
if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
gpios = variant_early_gpio_table(&num_gpios);
program_gpios(gpios, num_gpios);
}
printk(BIOS_DEBUG, "Bootblock configure eSPI\n");
dword = pci_read_config32(SOC_LPC_DEV, 0x78);
dword &= 0xFFFFF9F3;
dword |= 0x200;
pci_write_config32(SOC_LPC_DEV, 0x78, dword);
pci_write_config32(SOC_LPC_DEV, 0x44, 0);
pci_write_config32(SOC_LPC_DEV, 0x48, 0);
dword = pm_read32(0x90);
dword |= 1 << 16;
pm_write32(0x90, dword);
dword = pm_read32(0x74);
dword |= 3 << 10;
pm_write32(0x74, dword);
if (CONFIG(GPIO_SIGN_OF_LIFE)) {
for (int x = 0; x < 20; x++) {
gpio_set(GPIO_31, 1);
mdelay(10);
gpio_set(GPIO_31, 0);
mdelay(10);
}
}
if (variant_has_fpmcu())
variant_fpmcu_reset();
}
|