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path: root/src/mainboard/google/hatch/variants/puff/overridetree.cb
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chip soc/intel/cannonlake

	register "SerialIoDevMode" = "{
		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
		[PchSerialIoIndexSPI0] = PchSerialIoPci,
		[PchSerialIoIndexSPI1] = PchSerialIoPci,
		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
	}"

  # USB configuration
	register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)"
	register "usb2_ports[6]" = "USB2_PORT_EMPTY"
	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)"

	# Enable eMMC HS400
	register "ScsEmmcHs400Enabled" = "1"

	# EMMC Tx CMD Delay
	# Refer to EDS-Vol2-14.3.7.
	# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
	# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
	register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"

	# EMMC TX DATA Delay 1
	# Refer to EDS-Vol2-14.3.8.
	# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
	# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
	register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911"

	# EMMC TX DATA Delay 2
	# Refer to EDS-Vol2-14.3.9.
	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
	# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
	register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828"

	# EMMC RX CMD/DATA Delay 1
	# Refer to EDS-Vol2-14.3.10.
	# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
	# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
	# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
	# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b"

	# EMMC RX CMD/DATA Delay 2
	# Refer to EDS-Vol2-14.3.12.
	# [17:16] stands for Rx Clock before Output Buffer,
	#         00: Rx clock after output buffer,
	#         01: Rx clock before output buffer,
	#         10: Automatic selection based on working mode.
	#         11: Reserved
	# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
	# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
	register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D"

	# EMMC Rx Strobe Delay
	# Refer to EDS-Vol2-14.3.11.
	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
	register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515"

	# Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them.
	register "PchHdaAudioLinkSsp1" = "0"
	register "PchHdaAudioLinkDmic0" = "0"

	# Intel Common SoC Config
	#+-------------------+---------------------------+
	#| Field             |  Value                    |
	#+-------------------+---------------------------+
	#| GSPI0             | cr50 TPM. Early init is   |
	#|                   | required to set up a BAR  |
	#|                   | for TPM communication     |
	#|                   | before memory is up       |
	#| I2C0              | RFU                       |
	#| I2C2              | PS175                     |
	#| I2C3              | MST                       |
	#| I2C4              | Audio                     |
	#+-------------------+---------------------------+
	register "common_soc_config" = "{
		.gspi[0] = {
			.speed_mhz = 1,
			.early_init = 1,
		},
		.i2c[0] = {
			.speed = I2C_SPEED_FAST,
			.rise_time_ns = 0,
			.fall_time_ns = 0,
		},
		.i2c[2] = {
			.speed = I2C_SPEED_FAST,
			.rise_time_ns = 0,
			.fall_time_ns = 0,
		},
		.i2c[3] = {
			.speed = I2C_SPEED_FAST,
			.rise_time_ns = 0,
			.fall_time_ns = 0,
		},
		.i2c[4] = {
			.speed = I2C_SPEED_FAST,
			.rise_time_ns = 0,
			.fall_time_ns = 0,
		},
	}"

	# PCIe port 7 for LAN
	register "PcieRpEnable[6]" = "1"
	register "PcieRpLtrEnable[6]" = "1"
	# Uses CLK SRC 0
	register "PcieClkSrcUsage[0]" = "6"
	register "PcieClkSrcClkReq[0]" = "0"

	# GPIO for SD card detect
	register "sdcard_cd_gpio" = "vSD3_CD_B"

	device domain 0 on
		device pci 14.0 on
			chip drivers/usb/acpi
				device usb 0.0 on
					chip drivers/usb/acpi
						register "desc" = ""Type-A Port 4""
						register "type" = "UPC_TYPE_A"
						device usb 2.4 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Type-A Port 0""
						register "type" = "UPC_TYPE_A"
						device usb 2.5 on end
					end
					chip drivers/usb/acpi
						device usb 2.6 off end
					end
					chip drivers/usb/acpi
						register "desc" = ""Type-A Port 0""
						register "type" = "UPC_TYPE_USB3_A"
						device usb 3.4 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""Type-A Port 4""
						register "type" = "UPC_TYPE_USB3_A"
						device usb 3.5 on end
					end
				end
			end
		end # USB xHCI
		device pci 15.0 off
			# RFU - Reserved for Future Use.
		end # I2C #0
		device pci 15.1 off end # I2C #1
		device pci 15.2 on end # I2C #2, PCON PS175.
		device pci 15.3 on
#			chip drivers/i2c/generic
#				register "name" = ""RTD21""
#				register "desc" = ""Realtek RTD2142""
#				device i2c 4a on end
#			end
		end # I2C #3
		device pci 19.0 on
			chip drivers/i2c/generic
				register "hid" = ""10EC5682""
				register "name" = ""RT58""
				register "desc" = ""Realtek RT5682""
				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
				register "property_count" = "1"
				# Set the jd_src to RT5668_JD1 for jack detection
				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
				register "property_list[0].name" = ""realtek,jd-src""
				register "property_list[0].integer" = "1"
				device i2c 1a on end
			end
		end #I2C #4
		device pci 1a.0 on  end # eMMC
		device pci 1c.0 on  end # FSP requires func0 be enabled.
		device pci 1c.6 on  end # RTL8111H Ethernet NIC (becomes RP1).
		device pci 1e.3 off end # GSPI #1
	end

end