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path: root/src/mainboard/google/kahlee/ec.c
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/*
 * This file is part of the coreboot project.
 *
 * Copyright 2016 Google Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <arch/acpi.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
#include <rules.h>
#include <soc/southbridge.h>
#include <variant/ec.h>

static void ramstage_ec_init(void)
{
	const struct google_chromeec_event_info info = {
		.log_events = MAINBOARD_EC_LOG_EVENTS,
		.sci_events = MAINBOARD_EC_SCI_EVENTS,
		.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
	};

	printk(BIOS_DEBUG, "mainboard: EC init\n");

	google_chromeec_events_init(&info, acpi_is_wakeup_s3());
}

static void early_ec_init(void)
{
#ifdef __PRE_RAM__
	uint16_t ec_ioport_base;
	size_t ec_ioport_size;

	/*
	 * Set up LPC decoding for the ChromeEC I/O port ranges:
	 * - Ports 62/66, 60/64, and 200->208
	 *  -- set by hudson_lpc_decode() in pre
	 * - ChromeEC specific communication I/O ports.
	 */
	google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
	printk(BIOS_DEBUG,
		"LPC Setup google_chromeec_ioport_range: %04x, %08zx\n",
		ec_ioport_base, ec_ioport_size);
	lpc_wideio_512_window(ec_ioport_base);
#endif //_PRE_RAM_
}

void mainboard_ec_init(void)
{
	if (ENV_RAMSTAGE)
		ramstage_ec_init();
	else
		early_ec_init();
}