src/mainboard/google/mistral/romstage.c


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

/* This file is part of the coreboot project. */
/* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/stages.h>
#include <soc/usb.h>

static void prepare_usb(void)
{
	/*
	 * Do DWC3 core and phy reset. Kick these resets off early
	 * so they get atleast 1msec to settle.
	 */
	reset_usb(HSUSB_HS_PORT_1);
}

void platform_romstage_main(void)
{
	prepare_usb();
}