1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <armv7.h>
#include <cbfs.h>
#include <common.h>
#include <arch/cache.h>
#include <arch/gpio.h>
#include <cpu/samsung/exynos5-common/i2c.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/dmc.h>
#include <cpu/samsung/exynos5250/gpio.h>
#include <cpu/samsung/exynos5250/setup.h>
#include <cpu/samsung/exynos5250/periph.h>
#include <cpu/samsung/exynos5250/power.h>
#include <cpu/samsung/exynos5250/clock_init.h>
#include <console/console.h>
#include <arch/stages.h>
#include <time.h>
#include <drivers/maxim/max77686/max77686.h>
#include <device/i2c.h>
#include "mainboard.h"
#define PMIC_BUS 0
#define MMC0_GPIO_PIN (58)
#if 0
static int board_wakeup_permitted(void)
{
const int gpio = GPIO_Y10;
int is_bad_wake;
/* We're a bad wakeup if the gpio was defined and was high */
is_bad_wake = ((gpio != -1) && gpio_get_value(gpio));
return !is_bad_wake;
}
#endif
static int setup_pmic(void)
{
int error = 0;
/*
* We're using CR1616 coin cell battery that is non-rechargeable
* battery. But, BBCHOSTEN bit of the BBAT Charger Register in
* MAX77686 is enabled by default for charging coin cell.
*
* Also, we cannot meet the coin cell reverse current spec. in UL
* standard if BBCHOSTEN bit is enabled.
*
* Disable Coin BATT Charging
*/
error = max77686_disable_backup_batt(PMIC_BUS);
error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK2, CONFIG_VDD_ARM_MV,
REG_ENABLE, MAX77686_MV);
error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK3, CONFIG_VDD_INT_UV,
REG_ENABLE, MAX77686_UV);
error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK1, CONFIG_VDD_MIF_MV,
REG_ENABLE, MAX77686_MV);
error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK4, CONFIG_VDD_G3D_MV,
REG_ENABLE, MAX77686_MV);
error |= max77686_volsetting(PMIC_BUS, PMIC_LDO2, CONFIG_VDD_LDO2_MV,
REG_ENABLE, MAX77686_MV);
error |= max77686_volsetting(PMIC_BUS, PMIC_LDO3, CONFIG_VDD_LDO3_MV,
REG_ENABLE, MAX77686_MV);
error |= max77686_volsetting(PMIC_BUS, PMIC_LDO5, CONFIG_VDD_LDO5_MV,
REG_ENABLE, MAX77686_MV);
error |= max77686_volsetting(PMIC_BUS, PMIC_LDO10, CONFIG_VDD_LDO10_MV,
REG_ENABLE, MAX77686_MV);
if (error)
printk(BIOS_CRIT, "%s: Error during PMIC setup\n", __func__);
return error;
}
static void initialize_s5p_mshc(void)
{
/* MMC0: Fixed, 8 bit mode, connected with GPIO. */
if (clock_set_mshci(PERIPH_ID_SDMMC0))
printk(BIOS_CRIT, "Failed to set clock for SDMMC0.\n");
if (gpio_direction_output(MMC0_GPIO_PIN, 1)) {
printk(BIOS_CRIT, "Unable to power on SDMMC0.\n");
}
gpio_set_pull(MMC0_GPIO_PIN, EXYNOS_GPIO_PULL_NONE);
gpio_set_drv(MMC0_GPIO_PIN, EXYNOS_GPIO_DRV_4X);
exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
/* MMC2: Removable, 4 bit mode, no GPIO. */
clock_set_mshci(PERIPH_ID_SDMMC2);
exynos_pinmux_config(PERIPH_ID_SDMMC2, 0);
}
static void graphics(void)
{
exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
}
static void chromeos_gpios(void)
{
struct exynos5_gpio_part1 *gpio_pt1;
struct exynos5_gpio_part2 *gpio_pt2;
enum {
WP_GPIO = 6,
FORCE_RECOVERY_MODE = 0,
LID_OPEN = 5
};
gpio_pt1 = (struct exynos5_gpio_part1 *)EXYNOS5_GPIO_PART1_BASE;
gpio_pt2 = (struct exynos5_gpio_part2 *)EXYNOS5_GPIO_PART2_BASE;
s5p_gpio_direction_input(&gpio_pt1->d1, WP_GPIO);
s5p_gpio_set_pull(&gpio_pt1->d1, WP_GPIO, EXYNOS_GPIO_PULL_NONE);
s5p_gpio_direction_input(&gpio_pt1->y1, FORCE_RECOVERY_MODE);
s5p_gpio_set_pull(&gpio_pt1->y1, FORCE_RECOVERY_MODE,
EXYNOS_GPIO_PULL_NONE);
s5p_gpio_direction_input(&gpio_pt2->x3, LID_OPEN);
s5p_gpio_set_pull(&gpio_pt2->x3, LID_OPEN, EXYNOS_GPIO_PULL_NONE);
}
void main(void)
{
struct mem_timings *mem;
struct arm_clk_ratios *arm_ratios;
int ret;
void *entry;
clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
/* Clock must be initialized before console_init, otherwise you may need
* to re-initialize serial console drivers again. */
mem = get_mem_timings();
arm_ratios = get_arm_clk_ratios();
system_clock_init(mem, arm_ratios);
console_init();
i2c_init(0, CONFIG_SYS_I2C_SPEED, 0x00);
if (power_init())
power_shutdown();
printk(BIOS_DEBUG, "%s: setting up pmic...\n", __func__);
if (setup_pmic())
power_shutdown();
if (!mem) {
printk(BIOS_CRIT, "Unable to auto-detect memory timings\n");
while(1);
}
printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n",
mem->mem_manuf,
mem->mem_type,
mem->mpll_mdiv,
mem->frequency_mhz);
ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE);
if (ret) {
printk(BIOS_ERR, "Memory controller init failed, err: %x\n",
ret);
while(1);
}
initialize_s5p_mshc();
chromeos_gpios();
graphics();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);
stage_exit(entry);
}
|
