blob: 9c126fd76570109f7873c5c7a57ecb9ce302a093 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
|
##
## This file is part of the coreboot project.
##
## Copyright 2014 Rockchip Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config BOARD_GOOGLE_VEYRON # dummy option to be selected by variant boards
def_bool n
if BOARD_GOOGLE_VEYRON
# Some Veyron boards incorrectly had their RAM code strapped with 100Kohm
# resistors. These get overpowered by the SoC's internal pull-downs, so we
# cannot read those pins as tri-state. They're restricted to binary RAM codes.
config VEYRON_FORCE_BINARY_RAM_CODE
bool
default y if BOARD_GOOGLE_VEYRON_JAQ
default y if BOARD_GOOGLE_VEYRON_JERRY
default y if BOARD_GOOGLE_VEYRON_MIGHTY
default n
config BOARD_SPECIFIC_OPTIONS
def_bool y
select COMMON_CBFS_SPI_WRAPPER
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_SPI
select SOC_ROCKCHIP_RK3288
select MAINBOARD_HAS_CHROMEOS
select BOARD_ROMSIZE_KB_4096
select SPI_FLASH
select SPI_FLASH_GIGADEVICE
select SPI_FLASH_WINBOND
select MAINBOARD_HAS_I2C_TPM_GENERIC
select MAINBOARD_HAS_TPM1
config VBOOT
select VBOOT_VBNV_EC
config MAINBOARD_DIR
string
default google/veyron
config MAINBOARD_PART_NUMBER
string
default "Veyron_Jaq" if BOARD_GOOGLE_VEYRON_JAQ
default "Veyron_Jerry" if BOARD_GOOGLE_VEYRON_JERRY
default "Veyron_Mighty" if BOARD_GOOGLE_VEYRON_MIGHTY
default "Veyron_Minnie" if BOARD_GOOGLE_VEYRON_MINNIE
default "Veyron_Speedy" if BOARD_GOOGLE_VEYRON_SPEEDY
default "Veyron"
config MAINBOARD_VENDOR
string
default "Google"
config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
default 0x0
config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
int
default 100
config BOOT_DEVICE_SPI_FLASH_BUS
int
default 2
config DRIVER_TPM_I2C_BUS
hex
default 0x1
config DRIVER_TPM_I2C_ADDR
hex
default 0x20
config CONSOLE_SERIAL_UART_ADDRESS
hex
depends on DRIVERS_UART
default 0xFF690000
config PMIC_BUS
int
default 0
config CBFS_SIZE
hex
default 0x100000 if CHROMEOS
default ROM_SIZE
config EC_GOOGLE_CHROMEEC_BOARDNAME
string
depends on CHROMEOS
#default "jaq" if BOARD_GOOGLE_VEYRON_JAQ
default "jerry" if BOARD_GOOGLE_VEYRON_JERRY
#default "mighty" if BOARD_GOOGLE_VEYRON_MIGHTY
#default "minnie" if BOARD_GOOGLE_VEYRON_MINNIE
#default "speedy" if BOARD_GOOGLE_VEYRON_SPEEDY
config GBB_HWID
string
depends on CHROMEOS
default "JAQ TEST A-A 8292" if BOARD_GOOGLE_VEYRON_JAQ
default "JERRY TEST A-A 1250" if BOARD_GOOGLE_VEYRON_JERRY
default "MIGHTY TEST A-A 4557" if BOARD_GOOGLE_VEYRON_MIGHTY
default "MINNIE TEST A-A 5151" if BOARD_GOOGLE_VEYRON_MINNIE
default "SPEEDY TEST A-A 8421" if BOARD_GOOGLE_VEYRON_SPEEDY
endif # BOARD_GOOGLE_VEYRON
|
