summaryrefslogtreecommitdiff
path: root/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc
blob: 00dc5491615cf0315065620f1ccd2fc53701fe7e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
{
	/* 2 Hynix H9CCNNN8GTMLAR chips */
	{
		{
			.rank = 0x1,
			.col = 0xA,
			.bk = 0x3,
			.bw = 0x2,
			.dbw = 0x2,
			.row_3_4 = 0x0,
			.cs0_row = 0xF,
			.cs1_row = 0xF
		},
		{
			.rank = 0x1,
			.col = 0xA,
			.bk = 0x3,
			.bw = 0x2,
			.dbw = 0x2,
			.row_3_4 = 0x0,
			.cs0_row = 0xF,
			.cs1_row = 0xF
		}
	},
	{
		.togcnt1u = 0x215,
		.tinit = 0xC8,
		.trsth = 0x0,
		.togcnt100n = 0x35,
		.trefi = 0x26,
		.tmrd = 0x2,
		.trfc = 0x70,
		.trp = 0x2000D,
		.trtw = 0x6,
		.tal = 0x0,
		.tcl = 0x8,
		.tcwl = 0x4,
		.tras = 0x17,
		.trc = 0x24,
		.trcd = 0xD,
		.trrd = 0x6,
		.trtp = 0x4,
		.twr = 0x8,
		.twtr = 0x4,
		.texsr = 0x76,
		.txp = 0x4,
		.txpdll = 0x0,
		.tzqcs = 0x30,
		.tzqcsi = 0x0,
		.tdqs = 0x1,
		.tcksre = 0x2,
		.tcksrx = 0x2,
		.tcke = 0x4,
		.tmod = 0x0,
		.trstl = 0x0,
		.tzqcl = 0xC0,
		.tmrr = 0x4,
		.tckesr = 0x8,
		.tdpd = 0x1F4
	},
	{
		.dtpr0 = 0x48D7DD93,
		.dtpr1 = 0x187008D8,
		.dtpr2 = 0x121076,
		.mr[0] = 0x0,
		.mr[1] = 0xC3,
		.mr[2] = 0x6,
		.mr[3] = 0x1
	},
	.noc_timing = 0x20D266A4,
	.noc_activate = 0x5B6,
	.ddrconfig = 14,
	.ddr_freq = 533*MHz,
	.dramtype = LPDDR3,
	.num_channels = 2,
	.stride = 9,
	.odt = 0,
},