summaryrefslogtreecommitdiff
path: root/src/mainboard/hp/2570p/devicetree.cb
blob: 6dcfb616059d66d23507946fca158a05e14c640c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
#
# This file is part of the coreboot project.
#
# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#

chip northbridge/intel/sandybridge
	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
	register "gfx.link_frequency_270_mhz" = "1"
	register "gfx.ndid" = "3"
	register "gfx.use_spread_spectrum_clock" = "1"
	register "gpu_cpu_backlight" = "0x00000437"
	register "gpu_dp_b_hotplug" = "4"
	register "gpu_dp_c_hotplug" = "4"
	register "gpu_dp_d_hotplug" = "4"
	register "gpu_panel_port_select" = "0"
	register "gpu_panel_power_backlight_off_delay" = "2300"
	register "gpu_panel_power_backlight_on_delay" = "2000"
	register "gpu_panel_power_cycle_delay" = "5"
	register "gpu_panel_power_down_delay" = "230"
	register "gpu_panel_power_up_delay" = "300"
	register "gpu_pch_backlight" = "0x0d9c0d9c"
	device cpu_cluster 0x0 on
		chip cpu/intel/socket_rPGA989
			device lapic 0x0 on
			end
		end
		chip cpu/intel/model_206ax
			register "c1_acpower" = "1"
			register "c1_battery" = "1"
			register "c2_acpower" = "3"
			register "c2_battery" = "3"
			register "c3_acpower" = "5"
			register "c3_battery" = "5"
			device lapic 0xacac off
			end
		end
	end
	device domain 0x0 on
		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
			register "c2_latency" = "0x0065"
			register "docking_supported" = "0"
			register "gen1_dec" = "0x007c0201"
			register "gen2_dec" = "0x000c0101"
			register "gen3_dec" = "0x00fcfe01"
			register "gen4_dec" = "0x000402e9"
			register "gpi6_routing" = "2"
			register "p_cnt_throttling_supported" = "1"
			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
			register "pcie_port_coalesce" = "1"
			register "sata_interface_speed_support" = "0x3"
			register "sata_port_map" = "0x33"
			register "spi_lvscc" = "0x0"
			register "spi_uvscc" = "0x2005"
			register "superspeed_capable_ports" = "0x0000000f"
			register "xhci_overcurrent_mapping" = "0x00000c03"
			register "xhci_switchable_ports" = "0x0000000f"
			device pci 14.0 on # USB 3.0 Controller
				subsystemid 0x103c 0x17df
			end
			device pci 16.0 on # Management Engine Interface 1
				subsystemid 0x103c 0x17df
			end
			device pci 16.1 off # Management Engine Interface 2
			end
			device pci 16.2 off # Management Engine IDE-R
			end
			device pci 16.3 off # Management Engine KT
			end
			device pci 19.0 on # Intel Gigabit Ethernet
				subsystemid 0x103c 0x17df
			end
			device pci 1a.0 on # USB2 EHCI #2
				subsystemid 0x103c 0x17df
			end
			device pci 1b.0 on # High Definition Audio Audio controller
				subsystemid 0x103c 0x17df
			end
			device pci 1c.0 on # PCIe Port #1
				subsystemid 0x103c 0x17df
			end
			device pci 1c.1 on # PCIe Port #2
				subsystemid 0x103c 0x17df
			end
			device pci 1c.2 on # PCIe Port #3
				subsystemid 0x103c 0x17df
			end
			device pci 1c.3 on # PCIe Port #4
				subsystemid 0x103c 0x17df
			end
			device pci 1c.4 off # PCIe Port #5
			end
			device pci 1c.5 off # PCIe Port #6
			end
			device pci 1c.6 off # PCIe Port #7
			end
			device pci 1c.7 off # PCIe Port #8
			end
			device pci 1d.0 on # USB2 EHCI #1
				subsystemid 0x103c 0x17df
			end
			device pci 1e.0 off # PCI bridge
			end
			device pci 1f.0 on # LPC bridge PCI-LPC bridge
				subsystemid 0x103c 0x17df
				chip ec/hp/kbc1126
					register "ec_data_port" = "0x62"
					register "ec_cmd_port" = "0x66"
					register "ec_ctrl_reg" = "0x81"
					register "ec_fan_ctrl_value" = "0x4d"
					device pnp ff.1 off end
				end # kbc1126
			end
			device pci 1f.2 on # SATA Controller 1
				subsystemid 0x103c 0x17df
			end
			device pci 1f.3 off # SMBus
			end
			device pci 1f.5 off # SATA Controller 2
			end
			device pci 1f.6 off # Thermal
			end
		end
		device pci 00.0 on # Host bridge Host bridge
			subsystemid 0x103c 0x17df
		end
		device pci 01.0 off # PCIe Bridge for discrete graphics
		end
		device pci 02.0 on # Internal graphics VGA controller
			subsystemid 0x103c 0x17df
		end
	end
end