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# This file is part of the coreboot project.
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x00000129"
register "gpu_panel_power_backlight_off_delay" = "2000"
register "gpu_pch_backlight" = "0x02880288"
device domain 0x0 on
subsystemid 0x103c 0x162a inherit
device pci 01.0 off end # PCIe Bridge for discrete graphics
device pci 02.0 on end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
register "gen4_dec" = "0x007c0281"
register "gpi6_routing" = "2"
register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
register "sata_port_map" = "0x21"
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #2, ExpressCard
device pci 1c.2 on end # PCIe Port #3, SD/MMC
device pci 1c.3 on end # WLAN
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1c.6 on end # PCIe Port #7, WWAN
device pci 1c.7 off end # PCIe Port #8
device pci 1f.0 on # LPC bridge
chip ec/hp/kbc1126
register "ec_data_port" = "0x60"
register "ec_cmd_port" = "0x64"
register "ec_ctrl_reg" = "0xca"
register "ec_fan_ctrl_value" = "0x4d"
device pnp ff.1 off end
end
end
end
end
end
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