1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
|
#
# This file is part of the coreboot project.
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x00000129"
register "gpu_panel_power_backlight_off_delay" = "2000"
register "gpu_pch_backlight" = "0x02880288"
device domain 0x0 on
subsystemid 0x103c 0x161c inherit
device pci 01.0 on end # PCIe Bridge for discrete graphics
device pci 02.0 on end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen3_dec" = "0x00fcfe01"
register "gen4_dec" = "0x000402e9"
register "gpi6_routing" = "2"
register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
# HDD(0), ODD(1), docking(3,5), eSATA(4)
register "sata_port_map" = "0x3b"
device pci 16.3 on end # Management Engine KT
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #2, ExpressCard
device pci 1c.2 on end # PCIe Port #3, SD/MMC
device pci 1c.3 on end # PCIe Port #4, WLAN
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1c.6 on end # PCIe Port #7, WWAN
device pci 1c.7 on end # PCIe Port #8, NEC USB 3.0 Host Controller
device pci 1f.0 on # LPC bridge
chip ec/hp/kbc1126
register "ec_data_port" = "0x60"
register "ec_cmd_port" = "0x64"
register "ec_ctrl_reg" = "0xca"
register "ec_fan_ctrl_value" = "0x6b"
device pnp ff.1 off end
end
chip superio/smsc/lpc47n217
device pnp 4e.3 on # Parallel
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 4e.4 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.5 off end # COM2
end
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
end
end
end
|
