summaryrefslogtreecommitdiff
path: root/src/mainboard/iei/juki-511p/Config.lb
blob: fcc70fd7039b233dbc90ee66461a4c513c3484dd (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
##
default CONFIG_ROM_SIZE = 256 * 1024 
default CONFIG_ROM_SECTION_SIZE   = CONFIG_ROM_SIZE
default CONFIG_ROM_SECTION_OFFSET = 0

##
## Compute the start location and size size of
## The coreboot bootloader.
##
default CONFIG_PAYLOAD_SIZE            = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)

##
## Compute where this copy of coreboot will start in the boot rom
##
default CONFIG_ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE )

##
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## CONFIG_XIP_ROM_SIZE must be a power of 2.
## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
##
default CONFIG_XIP_ROM_SIZE=65536
default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )

##
## Set all of the defaults for an x86 architecture
##

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o

if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o

##
## Romcc output
##
makerule ./failover.E
	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end

makerule ./failover.inc
	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end

makerule ./auto.E 
	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc 
	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end

##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds

##
## Build our reset vector (This is where coreboot is entered)
##
mainboardinit cpu/x86/16bit/reset16.inc 
ldscript /cpu/x86/16bit/reset16.lds 

### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc

##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds

###
### O.k. We aren't just an intermediary anymore!
###

##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/amd/model_gx1/cpu_setup.inc
mainboardinit cpu/amd/model_gx1/gx_setup.inc
mainboardinit ./auto.inc

##
## Include the secondary Configuration files 
##
#dir /pc80
#config chip.h

chip northbridge/amd/gx1
  device pci_domain 0 on
    device pci 0.0 on end
      chip southbridge/amd/cs5530

        device pci 12.0 on
          chip superio/winbond/w83977f
            device pnp 3f0.0 on		# FDC
              irq 0x70 = 6
            end
            device pnp 3f0.1 on		# Parallel port
              io 0x60 = 0x378
              irq 0x70 = 7
            end
            device pnp 3f0.2 on		# COM1
              io 0x60 = 0x3f8
              irq 0x70 = 4
            end
            register "com1" = "{115200}"
            device pnp 3f0.3 on		# COM2
              io 0x60 = 0x2f8
              irq 0x70 = 3
            end
            register "com2" = "{115200}"
            device pnp 3f0.4 on		# RTC
              io 0x60 = 0x070
              irq 0x70 = 8
            end
            device pnp 3f0.5 on		# Keyboard
              io 0x60 = 0x60
              io 0x62 = 0x64
              irq 0x70 = 1		# Int  1 for PS/2 keyboard
              irq 0x72 = 12		# Int 12 for PS/2 mouse
            end
            device pnp 3f0.6 off	# IR
            end
            device pnp 3f0.7 off	# GPIO1
            end
            device pnp 3f0.8 off	# GPIO
            end
          end
        device pci 12.1 on end		# SMI
        device pci 12.2 on end		# IDE
        device pci 12.3 on end		# Audio
        device pci 12.4 on end		# VGA onboard

      end

      device pci 0e.0 on end		# ETH0
      device pci 13.0 on end		# USB

    end
  end

  chip cpu/amd/model_gx1
  end

end