1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
/* H4 : I2C0 SDA */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
/* H6 : I2C1 SDA */
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
/* B16 : I2C5 SDA */
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
/* H5 : I2C0 SCL */
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
/* H7 : I2C1 SCL */
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
/* B17 : I2C5 SCL */
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
/* C5 : WWAN_PERST_N */
PAD_CFG_GPO(GPP_C5, 1, PLTRST),
/* E5 : WWAN_PERST# */
PAD_CFG_GPO(GPP_E5, 1, PLTRST),
/* D15 : WWAN_DISABLE_N */
PAD_CFG_GPO(GPP_D15, 1, PLTRST),
/* D9 : WWAN_FCP_POWER_OFF_N */
PAD_CFG_GPO(GPP_D9, 1, PLTRST),
/* D10 : PCH_SSD_PWR_EN */
PAD_CFG_GPO(GPP_D10, 1, PLTRST),
/* H0 : PCH_SSD_RST# */
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
/* D16 : CPU_SSD_PWR_EN */
PAD_CFG_GPO(GPP_D16, 1, PLTRST),
/* H13 : CPU_SSD_RST# */
PAD_CFG_GPO(GPP_H13, 1, PLTRST),
/* DDP1/2/A/B CTRLCLK and CTRLDATA pins */
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_E23, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
/* HPD_1 (E14) and HPD_2 (A18) pins */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
/* GPIO pin for PCIE SRCCLKREQB */
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
/* CAM1_RST */
PAD_CFG_GPO(GPP_R5, 1, PLTRST),
/* CAM2_RST */
PAD_CFG_GPO(GPP_E15, 1, PLTRST),
/* CAM1_PWR_EN */
PAD_CFG_GPO(GPP_B23, 1, PLTRST),
/* CAM2_PWR_EN */
PAD_CFG_GPO(GPP_E16, 1, PLTRST),
/* IMGCLKOUT0 */
PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
/* IMGCLKOUT1 */
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
/* C16 : I2C0 SDA */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* S0 : SNDW1_CLK */
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
/* S1 : SNDW1_DATA */
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
/* S2 : SNDW2_CLK */
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
/* S3 : SNDW2_DATA */
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
/* S4 : SNDW3_CLK */
PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
/* S5 : SNDW3_DATA */
PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
/* S6 : SNDW4_CLK */
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
/* S7 : SNDW4_DATA */
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2)
};
void variant_configure_gpio_pads(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
};
const struct cros_gpio *variant_cros_gpios(size_t *num)
{
*num = ARRAY_SIZE(cros_gpios);
return cros_gpios;
}
|
