blob: 53a7b0f0d47d362e842a97377118799d0664821f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Intel Corp.
* (Written by Lijian Zhao <lijian.zhao@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, /* DSDT revision: ACPI v2.0 */
"COREv4", /* OEM id */
"COREBOOT", /* OEM table id */
0x20110725 /* OEM revision */
)
{
Scope (\_SB) {
Device (PCI0)
{
Name (_HID, EISAID ("PNP0A08")) /* PCIe */
}
}
/* Chipset specific sleep states */
#include <soc/intel/apollolake/acpi/sleepstates.asl>
}
|
