blob: 989b5cd4ea282be4df06ec19eb974ab83e4c15d9 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
|
chip soc/intel/cannonlake
device cpu_cluster 0 on
device lapic 0 on end
end
# FSP configuration
register "RMT" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC6)"
register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[6]" = "USB2_PORT_MID(OC1)"
register "usb2_ports[7]" = "USB2_PORT_MID(OC1)"
register "usb2_ports[8]" = "USB2_PORT_MID(OC2)"
register "usb2_ports[9]" = "USB2_PORT_MID(OC7)"
register "usb2_ports[10]" = "USB2_PORT_MID(OC7)"
register "usb2_ports[11]" = "USB2_PORT_MID(OC3)"
register "usb2_ports[12]" = "USB2_PORT_MID(OC3)"
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC7)"
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)"
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC1)"
register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC1)"
register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)"
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC7)"
register "SataSalpSupport" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsEnable[2]" = "1"
register "SataPortsEnable[3]" = "1"
register "SataPortsEnable[4]" = "1"
register "SataPortsEnable[5]" = "1"
register "SataPortsEnable[6]" = "1"
register "SataPortsEnable[7]" = "1"
register "PchHdaDspEnable" = "0"
register "PchHdaAudioLinkHda" = "1"
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[5]" = "0"
register "PcieRpEnable[6]" = "0"
register "PcieRpEnable[7]" = "0"
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[9]" = "1"
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[11]" = "1"
register "PcieRpEnable[12]" = "0"
register "PcieRpEnable[13]" = "0"
register "PcieRpEnable[14]" = "0"
register "PcieRpEnable[15]" = "0"
register "PcieRpEnable[16]" = "0"
register "PcieRpEnable[17]" = "0"
register "PcieRpEnable[18]" = "0"
register "PcieRpEnable[19]" = "0"
register "PcieRpEnable[20]" = "0"
register "PcieRpEnable[21]" = "0"
register "PcieRpEnable[22]" = "0"
register "PcieRpEnable[23]" = "0"
register "PcieClkSrcUsage[0]" = "1"
register "PcieClkSrcUsage[1]" = "8"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[3]" = "0x6"
register "PcieClkSrcUsage[4]" = "0x18"
register "PcieClkSrcUsage[5]" = "14"
register "PcieClkSrcUsage[8]" = "0x40"
register "PcieClkSrcUsage[9]" = "PCIE_CLK_LAN"
register "PcieClkSrcClkReq[0]" = "0"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieClkSrcClkReq[3]" = "3"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieClkSrcClkReq[5]" = "5"
register "PcieClkSrcClkReq[8]" = "8"
register "PcieClkSrcClkReq[9]" = "9"
device domain 0 on
device pci 15.0 on end # I2C #0
device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 17.0 on end # SATA
device pci 19.0 off end # I2C #4 (Not available on PCH-H)
device pci 19.1 off end # I2C #5 (Not available on PCH-H)
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.4 off end # PCI Express Port 13
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15
device pci 1d.7 off end # PCI Express Port 16
device pci 1b.0 off end # PCI Express Port 17
device pci 1b.1 off end # PCI Express Port 18
device pci 1b.2 off end # PCI Express Port 19
device pci 1b.3 off end # PCI Express Port 20
device pci 1b.4 off end # PCI Express Port 21
device pci 1b.5 off end # PCI Express Port 22
device pci 1b.6 off end # PCI Express Port 23
device pci 1b.7 off end # PCI Express Port 24
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.6 on end # GbE
end
end
|
