summaryrefslogtreecommitdiff
path: root/src/mainboard/intel/d810e2cb/devicetree.cb
blob: 412933632d92923f6e08a68f50031fa168371549 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

chip northbridge/intel/i82810           # Northbridge
  device lapic_cluster 0 on              # APIC cluster
    chip cpu/intel/socket_FC_PGA370      # CPU
      device lapic 0 on end              # APIC
    end
  end
  device pci_domain 0 on                # PCI domain
    device pci 0.0 on end               # Graphics Memory Controller Hub (GMCH)
    device pci 1.0 on end		# Chipset Graphics Controller (CGC)
    chip southbridge/intel/i82801bx     # Southbridge
      register "pirqa_routing" = "0x05"
      register "pirqb_routing" = "0x06"
      register "pirqc_routing" = "0x07"
      register "pirqd_routing" = "0x09"
      register "pirqe_routing" = "0x0a"
      register "pirqf_routing" = "0x80"
      register "pirqg_routing" = "0x80"
      register "pirqh_routing" = "0x0b"

      register "ide0_enable" = "1"
      register "ide1_enable" = "1"

      device pci 1e.0 on end		# PCI bridge
      device pci 1f.0 on                # ISA bridge
        chip superio/smsc/smscsuperio   # Super I/O (SMSC LPC47M102)
          device pnp 4e.0 on            # Floppy
            io 0x60 = 0x3f0
            irq 0x70 = 6
            drq 0x74 = 2
          end
          device pnp 4e.3 on            # Parallel port
            io 0x60 = 0x378
            irq 0x70 = 7
            drq 0x74 = 4
          end
          device pnp 4e.4 on            # COM1
            io 0x60 = 0x3f8
            irq 0x70 = 4
          end
          device pnp 4e.5 off end       # COM2
          device pnp 4e.7 on            # PS/2 keyboard / mouse
            io 0x60 = 0x60
            io 0x62 = 0x64
            irq 0x70 = 1                # PS/2 keyboard interrupt
            irq 0x72 = 12               # PS/2 mouse interrupt
          end
          device pnp 4e.9 off end       # Game port
          device pnp 4e.a on            # Runtime registers
            io 0x60 = 0x800
          end
          device pnp 4e.b off end       # MPU-401
        end
      end
      device pci 1f.1 on end            # IDE
      device pci 1f.2 on end            # USB
      device pci 1f.3 on end            # SMbus
      device pci 1f.4 on end            # USB
      device pci 1f.5 on end            # Audio controller
      device pci 1f.6 off end           # Modem controller
    end
  end
end