blob: df33a0ff51b98ecfd10388c320af5c8be6862275 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
|
#
# This file is part of the coreboot project.
#
# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
if BOARD_INTEL_DG41WV
config BOARD_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_LGA775
select NORTHBRIDGE_INTEL_X4X
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_WINBOND_W83627DHG
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select INTEL_EDID
select MAINBOARD_HAS_NATIVE_VGA_INIT
select PCIEXP_ASPM
select PCIEXP_CLK_PM
select PCIEXP_L1_SUB_STATE
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select DRIVERS_I2C_CK505
select INTEL_GMA_HAVE_VBT
select MAINBOARD_HAS_LIBGFXINIT
config MAINBOARD_DIR
string
default "intel/dg41wv"
config MAINBOARD_PART_NUMBER
string
default "DG41WV"
config MAX_CPUS
int
default 4
endif # BOARD_INTEL_DG41WV
|
