summaryrefslogtreecommitdiff
path: root/src/mainboard/intel/emeraldlake2/gpio.h
blob: 81bccdfb03881771e4660b5cad6318426e49ced9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
/*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef EMERALDLAKE2_GPIO_H
#define EMERALDLAKE2_GPIO_H

#include "southbridge/intel/bd82x6x/gpio.h"

const struct pch_gpio_set1 pch_gpio_set1_mode = {
        .gpio0 = GPIO_MODE_GPIO,
        .gpio1 = GPIO_MODE_GPIO,
        .gpio3 = GPIO_MODE_GPIO,
        .gpio5 = GPIO_MODE_GPIO,
        .gpio6 = GPIO_MODE_GPIO,
        .gpio7 = GPIO_MODE_GPIO,
        .gpio8 = GPIO_MODE_GPIO,
        .gpio9 = GPIO_MODE_GPIO,
        .gpio12 = GPIO_MODE_GPIO,
        .gpio15 = GPIO_MODE_GPIO,
        .gpio21 = GPIO_MODE_GPIO,
	.gpio22 = GPIO_MODE_GPIO,
        .gpio24 = GPIO_MODE_GPIO,
        .gpio27 = GPIO_MODE_GPIO,
        .gpio28 = GPIO_MODE_GPIO,
};

const struct pch_gpio_set1 pch_gpio_set1_direction = {
        .gpio0 = GPIO_DIR_INPUT,
        .gpio3 = GPIO_DIR_INPUT,
        .gpio5 = GPIO_DIR_INPUT,
        .gpio7 = GPIO_DIR_INPUT,
        .gpio8 = GPIO_DIR_INPUT,
        .gpio9 = GPIO_DIR_INPUT,
        .gpio12 = GPIO_DIR_INPUT,
        .gpio15 = GPIO_DIR_INPUT,
        .gpio21 = GPIO_DIR_INPUT,
	.gpio22 = GPIO_DIR_INPUT,
        .gpio27 = GPIO_DIR_INPUT,
};

const struct pch_gpio_set1 pch_gpio_set1_level = {
};

const struct pch_gpio_set1 pch_gpio_set1_invert = {
};

const struct pch_gpio_set2 pch_gpio_set2_mode = {
        .gpio36 = GPIO_MODE_GPIO,
	.gpio48 = GPIO_MODE_GPIO,
        .gpio57 = GPIO_MODE_GPIO,
        .gpio60 = GPIO_MODE_GPIO,
};

const struct pch_gpio_set2 pch_gpio_set2_direction = {
	.gpio48 = GPIO_DIR_INPUT,
        .gpio57 = GPIO_DIR_INPUT,
};

const struct pch_gpio_set2 pch_gpio_set2_level = {
};

const struct pch_gpio_set3 pch_gpio_set3_mode = {
};

const struct pch_gpio_set3 pch_gpio_set3_direction = {
};

const struct pch_gpio_set3 pch_gpio_set3_level = {
};

const struct pch_gpio_map emeraldlake2_gpio_map = {
	.set1 = {
		.mode      = &pch_gpio_set1_mode,
		.direction = &pch_gpio_set1_direction,
		.level     = &pch_gpio_set1_level,
		.invert    = &pch_gpio_set1_invert,
	},
	.set2 = {
		.mode      = &pch_gpio_set2_mode,
		.direction = &pch_gpio_set2_direction,
		.level     = &pch_gpio_set2_level,
	},
	.set3 = {
		.mode      = &pch_gpio_set3_mode,
		.direction = &pch_gpio_set3_direction,
		.level     = &pch_gpio_set3_level,
	},
};

#endif