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path: root/src/mainboard/intel/glkrvp/chromeos.fmd
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FLASH 16M {
	WP_RO@0x0 0x400000 {
		SI_DESC@0x0 0x1000
		IFWI@0x1000 0x1ff000
		RO_VPD@0x200000 0x4000
		RO_SECTION@0x204000 0x1fc000 {
			FMAP@0x0 0x800
			RO_FRID@0x800 0x40
			RO_FRID_PAD@0x840 0x7c0
			COREBOOT(CBFS)@0x1000 0x1ab000
			GBB@0x1ac000 0x40000
			RO_UNUSED@0x1ec000 0x10000
		}
	}
	MISC_RW@0x400000 0x4a000 {
        UNIFIED_MRC_CACHE@0x0 0x31000 {
            RECOVERY_MRC_CACHE@0x0 0x10000
            RW_MRC_CACHE@0x10000 0x20000
            RW_VAR_MRC_CACHE@0x30000 0x1000
        }
		RW_ELOG@0x31000 0x4000
		RW_SHARED@0x35000 0x4000 {
			SHARED_DATA@0x0 0x2000
			VBLOCK_DEV@0x2000 0x2000
		}
		RW_VPD@0x39000 0x2000
		FPF_STATUS@0x3B000 0x1000
		TMP_UNUSED_HOLE@0x3C000 0xE000
	}
	RW_SECTION_A@0x44a000 0x477800 {
		VBLOCK_A@0x0 0x10000
		FW_MAIN_A(CBFS)@0x10000 0x4677c0
		RW_FWID_A@0x4777c0 0x40
	}
	RW_SECTION_B@0x8c1800 0x477800 {
		VBLOCK_B@0x0 0x10000
		FW_MAIN_B(CBFS)@0x10000 0x4677c0
		RW_FWID_B@0x4777c0 0x40
	}
	RW_NVRAM@0xd39000 0x6000
	SMMSTORE@0xd40000 0x40000
	RW_LEGACY(CBFS)@0xd80000 0x1b0000
	BIOS_UNUSABLE@0xf3f000 0x40000
	DEVICE_EXTENSION@0xf7f000 0x80000
	# Currently, it is required that the BIOS region be a multiple of 8KiB.
	# This is required so that the recovery mechanism can find SIGN_CSE
	# region aligned to 4K at the center of BIOS region. Since the
	# descriptor at the beginning uses 4K and BIOS starts at an offset of
	# 4K, a hole of 4K is created towards the end of the flash to compensate
	# for the size requirement of BIOS region.
	# FIT tool thus creates descriptor with following regions:
	# Descriptor --> 0 to 4K
	# BIOS       --> 4K to 0xf7f000
	# Device ext --> 0xf7f000 to 0xfff000
	UNUSED_HOLE@0xfff000 0x1000
}