summaryrefslogtreecommitdiff
path: root/src/mainboard/intel/kblrvp/dsdt.asl
blob: 953121985bdfce276042c6235a25f580863af0b3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
/*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2007-2009 coresystems GmbH
 * Copyright (C) 2015 Google Inc.
 * Copyright (C) 2016 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

DefinitionBlock(
	"dsdt.aml",
	"DSDT",
	0x05,		// DSDT revision: ACPI v5.0
	"COREv4",	// OEM id
	"COREBOOT",	// OEM table id
	0x20110725	// OEM revision
)
{
	// Some generic macros
	#include <soc/intel/skylake/acpi/platform.asl>

	// global NVS and variables
	#include <soc/intel/skylake/acpi/globalnvs.asl>

	// CPU
	#include <soc/intel/skylake/acpi/cpu.asl>

	Scope (\_SB) {
		Device (PCI0)
		{
                        /* Image processing unit */
                        #include <soc/intel/skylake/acpi/ipu.asl>
			#include <soc/intel/skylake/acpi/systemagent.asl>
			#include <soc/intel/skylake/acpi/pch.asl>
		}

		// Dynamic Platform Thermal Framework
		#include "acpi/dptf.asl"
	}

	/* MIPI camera */
	#include "acpi/ipu_mainboard.asl"
	#include "acpi/mipi_camera.asl"

#if IS_ENABLED(CONFIG_CHROMEOS)
	// Chrome OS specific
	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif

	// Chipset specific sleep states
	#include <soc/intel/skylake/acpi/sleepstates.asl>

	// Mainboard specific
	#include "acpi/mainboard.asl"
}