1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
|
chip soc/intel/skylake
# SATA port 0
register "EnableSata" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsEnable[2]" = "1"
# Enable deep Sx states
register "deep_s5_enable_ac" = "1"
register "deep_s5_enable_dc" = "1"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen2_dec" = "0x000c0201"
# FSP Configuration
register "HeciEnabled" = "0"
register "PmTimerDisabled" = "1"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
#+----------------+-------+-------+-------+-------+
#| Psi1Threshold | 20A | 20A | 20A | 20A |
#| Psi2Threshold | 5A | 5A | 5A | 5A |
#| Psi3Threshold | 1A | 1A | 1A | 1A |
#| Psi3Enable | 1 | 1 | 1 | 1 |
#| Psi4Enable | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 |
#| IccMax | Auto | Auto | Auto | Auto |
#| VrVoltageLimit*| 0 | 0 | 0 | 0 |
#+----------------+-------+-------+-------+-------+
#* VrVoltageLimit command not sent.
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = 0, \
.voltage_limit = 0 \
}"
register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = 0, \
.voltage_limit = 0 \
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = 0 ,\
.voltage_limit = 0 \
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
.vr_config_enable = 1, \
.psi1threshold = VR_CFG_AMP(20), \
.psi2threshold = VR_CFG_AMP(5), \
.psi3threshold = VR_CFG_AMP(1), \
.psi3enable = 1, \
.psi4enable = 1, \
.imon_slope = 0, \
.imon_offset = 0, \
.icc_max = 0, \
.voltage_limit = 0 \
}"
# Enable Root ports.
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[8]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[2]" = "1"
register "PcieRpClkReqSupport[3]" = "1"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqSupport[5]" = "1"
register "PcieRpClkReqSupport[8]" = "1"
# RP 3 uses SRCCLKREQ5#
register "PcieRpClkReqNumber[2]" = "5"
register "PcieRpClkReqNumber[3]" = "2"
register "PcieRpClkReqNumber[4]" = "3"
register "PcieRpClkReqNumber[5]" = "4"
register "PcieRpClkReqNumber[8]" = "1"
# RP 3 uses uses CLK SRC 5#
register "PcieRpClkSrcNumber[2]" = "5"
# RP 4 uses uses CLK SRC 2#
register "PcieRpClkSrcNumber[3]" = "2"
# RP 5 uses uses CLK SRC 3#
register "PcieRpClkSrcNumber[4]" = "3"
# RP 6 uses uses CLK SRC 4#
register "PcieRpClkSrcNumber[5]" = "4"
# RP 9 uses uses CLK SRC 1#
register "PcieRpClkSrcNumber[8]" = "1"
# USB 2.0 Enable all ports
register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port
register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-A Port
register "usb2_ports[5]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
register "usb2_ports[6]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
register "usb2_ports[7]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
register "usb2_ports[9]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
# USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoPci, \
[PchSerialIoIndexI2C1] = PchSerialIoPci, \
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C4] = PchSerialIoPci, \
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
}"
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_G5"
# Lock Down
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 17.0 on end # SATA
device pci 19.1 off end # I2C #5
device pci 1c.2 on end # PCI Express Port 3
device pci 1c.3 on end # PCI Express Port 4
device pci 1c.4 on end # PCI Express Port 5
device pci 1c.5 on end # PCI Express Port 6
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end # LPC Interface
end
end
|
