summaryrefslogtreecommitdiff
path: root/src/mainboard/intel/mohonpeak/Kconfig
blob: eb97663c7a4d08fe6324337b6672c816dab62205 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
##
## This file is part of the coreboot project.
##
## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##

if BOARD_INTEL_MOHONPEAK

config BOARD_SPECIFIC_OPTIONS # dummy
	def_bool y
	select CPU_INTEL_SOCKET_RPGA989
	select NORTHBRIDGE_INTEL_FSP_RANGELEY
	select SOUTHBRIDGE_INTEL_FSP_RANGELEY
	select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB
	select HAVE_ACPI_TABLES
	select HAVE_OPTION_TABLE
	select MMCONF_SUPPORT
	select POST_IO
	select DEFAULT_POST_DEVICE_LPC
	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT

config MAINBOARD_DIR
	string
	default intel/mohonpeak

config INCLUDE_ME
	bool
	default n

config LOCK_MANAGEMENT_ENGINE
	bool
	default n

config MAINBOARD_PART_NUMBER
	string
	default "Mohon Peak CRB"

config IRQ_SLOT_COUNT
	int
	default 18

config MAX_CPUS
	int
	default 16

config CACHE_ROM_SIZE_OVERRIDE
	hex
	default 0x800000

config FSP_FILE
	string
	default "../intel/fsp/rangeley/FvFsp.bin"

config CBFS_SIZE
	hex
	default 0x00200000

config DRIVERS_PS2_KEYBOARD
	bool
	default n

config CONSOLE_POST
	bool
	default y

config ENABLE_FSP_FAST_BOOT
	bool
	depends on HAVE_FSP_BIN
	default y

config VIRTUAL_ROM_SIZE
	hex
	depends on ENABLE_FSP_FAST_BOOT
	default 0x400000

config FSP_PACKAGE_DEFAULT
	bool "Configure defaults for the Intel FSP package"
	default n

config UART_FOR_CONSOLE
	int
	default 1
	help
	  The Mohon Peak board uses COM2 (2f8) for the serial console.

config SEABIOS_MALLOC_UPPERMEMORY
	bool
	default n
	help
	  The Avoton/Rangeley chip does not allow devices to write into the 0xe000
	  segment.  This means that USB/SATA devices will not work in SeaBIOS unless
	  we put the SeaBIOS buffer area down in the 0x9000 segment.

endif # BOARD_INTEL_MOHONPEAK