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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
* Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <ec/acpi/ec.h>
#include <southbridge/intel/ibexpeak/pch.h>
#include <northbridge/intel/nehalem/nehalem.h>
void mainboard_lpc_init(void)
{
/* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
COMA_LPC_EN | GAMEL_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0);
pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8);
pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
(pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1);
pci_write_config32(PCH_LPC_DEV, ETR3,
pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR);
/* Enable USB Power. We need to do it early for usbdebug to work. */
ec_set_bit(0x3b, 4);
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
/* Enabled, Current table lookup index, OC map */
{ 1, IF1_557, 0 },
{ 1, IF1_55F, 1 },
{ 1, IF1_74B, 3 },
{ 1, IF1_74B, 3 },
{ 1, IF1_557, 3 },
{ 1, IF1_14B, 3 },
{ 1, IF1_74B, 3 },
{ 1, IF1_74B, 3 },
{ 1, IF1_74B, 4 },
{ 1, IF1_74B, 5 },
{ 1, IF1_55F, 7 },
{ 1, IF1_55F, 7 },
{ 1, IF1_557, 7 },
{ 1, IF1_55F, 7 },
};
static void set_fsb_frequency(void)
{
u8 block[5];
u16 fsbfreq = 62879;
smbus_block_read(0x69, 0, 5, block);
block[0] = fsbfreq;
block[1] = fsbfreq >> 8;
smbus_block_write(0x69, 0, 5, block);
}
void mainboard_pre_raminit(void)
{
outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20,
DEFAULT_GPIOBASE | 0x3a);
outb(0x50, 0x15ec);
outb(inb(0x15ee) & 0x70, 0x15ee);
set_fsb_frequency();
}
void mainboard_get_spd_map(u8 *spd_addrmap)
{
spd_addrmap[0] = 0x50;
spd_addrmap[2] = 0x51;
}
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