summaryrefslogtreecommitdiff
path: root/src/mainboard/lenovo/x60/devicetree.cb
blob: 55e0b2d4990dd52217fdc53eeba3fe59d2d5b1d8 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
## MA 02110-1301 USA
##

chip northbridge/intel/i945

	device lapic_cluster 0 on
		chip cpu/intel/socket_mFCPGA478
			device lapic 0 on end
		end
	end

	device pci_domain 0 on
		device pci 00.0 on # Host bridge
			subsystemid 0x17aa 0x2017
		end
		device pci 02.0 on # VGA controller
			subsystemid 0x17aa 0x201a
		end
		device pci 02.1 on # display controller
			subsystemid 0x17aa 0x201a
		end
		chip southbridge/intel/i82801gx
			register "pirqa_routing" = "0x0b"
			register "pirqb_routing" = "0x0b"
			register "pirqc_routing" = "0x0b"
			register "pirqd_routing" = "0x0b"
			register "pirqe_routing" = "0x0b"
			register "pirqf_routing" = "0x0b"
			register "pirqg_routing" = "0x0b"
			register "pirqh_routing" = "0x0b"

			# GPI routing
			#  0 No effect (default)
			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
			#  2 SCI (if corresponding GPIO_EN bit is also set)
			register "gpi13_routing" = "2"
			register "gpi12_routing" = "1"
			register "gpi8_routing" = "2"

			register "sata_ahci" = "0x0"

			register "gpe0_en" = "0x11000006"
			register "alt_gp_smi_en" = "0x1000"
			device pci 1b.0 on # Audio Cnotroller
				subsystemid 0x17aa 0x2010
			end
			device pci 1c.0 on end # Ethernet
			device pci 1c.1 on end # Atheros WLAN
			device pci 1d.0 on # USB UHCI
				subsystemid 0x17aa 0x200a
			end
			device pci 1d.1 on # USB UHCI
				subsystemid 0x17aa 0x200a
			end
			device pci 1d.2 on # USB UHCI
				subsystemid 0x17aa 0x200a
			end
			device pci 1d.3 on # USB UHCI
				subsystemid 0x17aa 0x200a
			end
			device pci 1d.7 on # USB2 EHCI
				subsystemid 0x17aa 0x200b
			end
			device pci 1f.0 on # PCI-LPC bridge
				subsystemid 0x17aa 0x2009
				chip ec/lenovo/pmh7
					device pnp ff.1 on # dummy
					end
					register "backlight_enable" = "0x01"
					register "dock_event_enable" = "0x01"
				end
				chip ec/lenovo/h8
					device pnp ff.2 on # dummy
						io 0x60 = 0x62
						io 0x62 = 0x66
						io 0x64 = 0x1600
						io 0x66 = 0x1604
					end

					register "config0" = "0xa6"
					register "config1" = "0x05"
					register "config2" = "0xa0"
					register "config3" = "0x01"

					register "beepmask0" = "0xfe"
					register "beepmask1" = "0x96"

					register "event2_enable" = "0xff"
					register "event3_enable" = "0xff"
					register "event4_enable" = "0xf4"
					register "event5_enable" = "0x3c"
					register "event6_enable" = "0x80"
					register "event7_enable" = "0x01"
					register "eventc_enable" = "0x3c"
					register "event8_enable" = "0x01"
					register "event9_enable" = "0xff"
					register "eventa_enable" = "0xff"
					register "eventb_enable" = "0xff"
					register "eventc_enable" = "0xff"
					register "eventd_enable" = "0xff"

					register "wlan_enable" = "0x01"
					register "trackpoint_enable" = "0x03"
				end
				chip superio/nsc/pc87382
					device pnp 164e.2 on # IR
						io 0x60 = 0x2f8
					end

					device pnp 164e.3 off # Serial Port
						io 0x60 = 0x3f8
					end

					device pnp 164e.7 on # GPIO
						io 0x60 = 0x1680
					end

					device pnp 164e.19 on # DLPC
						io 0x60 = 0x164c
					end
				end

				chip superio/nsc/pc87392
					device pnp 2e.0 off #FDC
					end

					device pnp 2e.1 on # Parallel Port
						io 0x60 = 0x3bc
						irq 0x70 = 7
					end

					device pnp 2e.2 off # Serial Port / IR
						io 0x60 = 0x2f8
						irq 0x70 = 4
					end

					device pnp 2e.3 on # Serial Port
						io 0x60 = 0x3f8
						irq 0x70 = 4
					end

					device pnp 2e.7 on # GPIO
						io 0x60 = 0x1620
					end

					device pnp 2e.a off # WDT
					end
				end
			end
			device pci 1f.1 on # IDE
				subsystemid 0x17aa 0x200c
			end
			device pci 1f.2 on # SATA
				subsystemid 0x17aa 0x200d
			end
			device pci 1f.3 on # SMBUS
				subsystemid 0x17aa 0x200f
			end
		end
		chip southbridge/ricoh/rl5c476
		end
	end
end