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##
## This file is part of the coreboot project.
##
##
## SPDX-License-Identifier: GPL-2.0-only
if BOARD_OPENCELLULAR_ELGON
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select COMMON_CBFS_SPI_WRAPPER
select RTC
select SOC_CAVIUM_CN81XX
select SPI_FLASH
select SPI_FLASH_WINBOND
select MAINBOARD_HAS_I2C_TPM_GENERIC
select MAINBOARD_HAS_TPM1
select MISSING_BOARD_RESET
config VBOOT
select VBOOT_NO_BOARD_SUPPORT
select GBB_FLAG_DISABLE_LID_SHUTDOWN
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_FWMP
config GBB_HWID
string
depends on VBOOT
default "ELGON"
config MAINBOARD_DIR
string
default "opencellular/elgon"
config DRIVER_TPM_I2C_BUS
hex
default 0x1
config DRIVER_TPM_I2C_ADDR
hex
default 0x20
config DRAM_SIZE_MB
int
default 4096
config BOOT_DEVICE_SPI_FLASH_BUS
int
default 0
config CONSOLE_SERIAL_UART_ADDRESS
hex
depends on DRIVERS_UART
default 0x87E028000000
config UART_FOR_CONSOLE
int
depends on DRIVERS_UART
default 0
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot.fmd" if VBOOT
config MAX_CPUS
default 4
##########################################################
#### Update below when adding a new derivative board. ####
##########################################################
config MAINBOARD_PART_NUMBER
string
default "Elgon"
config MAINBOARD_FIT_DTS
string
default "gbcv2.dts"
endif
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