summaryrefslogtreecommitdiff
path: root/src/mainboard/protectli/vault_kbl/devicetree.cb
blob: d3e8b2305c70ce43b504c6c477ae9b5af50bcc07 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
chip soc/intel/skylake

	# Enable deep Sx states
	register "deep_s3_enable_ac" = "0"
	register "deep_s3_enable_dc" = "0"
	register "deep_s5_enable_ac" = "1"
	register "deep_s5_enable_dc" = "1"
	register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
	register "s0ix_enable" = "1"

	register "gpe0_dw0" = "GPP_B"
	register "gpe0_dw1" = "GPP_D"
	register "gpe0_dw2" = "GPP_E"

	register "gen1_dec" = "0x00fc0201"
	register "gen2_dec" = "0x007c0a01"
	register "gen3_dec" = "0x000c03e1"
	register "gen4_dec" = "0x001c02e1"

	# Enable "Intel Speed Shift Technology"
	register "speed_shift_enable" = "1"
	register "eist_enable" = "1"

	# Disable DPTF
	register "dptf_enable" = "0"

	# Enable VT-d
	register "ignore_vtd" = "0"

	# Enable SERIRQ continuous
	register "serirq_mode" = "SERIRQ_CONTINUOUS"

	register "tcc_offset" = "5" # TCC of 95C

	# FSP Configuration
	register "ProbelessTrace" = "0"
	register "EnableLan" = "0"
	register "EnableSata" = "1"
	register "SataSalpSupport" = "0"
	register "SataMode" = "0"
	register "EnableAzalia" = "0"
	register "DspEnable" = "0"
	register "IoBufferOwnership" = "0"
	register "EnableTraceHub" = "0"
	register "SsicPortEnable" = "0"
	register "SmbusEnable" = "1"
	register "Cio2Enable" = "0"
	register "ScsEmmcEnabled" = "0"
	register "ScsEmmcHs400Enabled" = "0"
	register "ScsSdCardEnabled" = "0"
	register "SkipExtGfxScan" = "1"
	register "Device4Enable" = "0"
	register "HeciEnabled" = "1"
	register "PmTimerDisabled" = "1"
	register "SaGv" = "SaGv_Enabled"
	register "SaImguEnable" = "0"
	register "IslVrCmd" = "2"
	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
	register "PmConfigSlpS4MinAssert" = "4"		# 4s
	register "PmConfigSlpSusMinAssert" = "1"	# 500ms
	register "PmConfigSlpAMinAssert" = "3"		# 2s

	register "pirqa_routing" = "PCH_IRQ11"
	register "pirqb_routing" = "PCH_IRQ10"
	register "pirqc_routing" = "PCH_IRQ11"
	register "pirqd_routing" = "PCH_IRQ11"
	register "pirqe_routing" = "PCH_IRQ11"
	register "pirqf_routing" = "PCH_IRQ11"
	register "pirqg_routing" = "PCH_IRQ11"
	register "pirqh_routing" = "PCH_IRQ11"

	# VR Settings Configuration for 4 Domains
	#+----------------+-------+-------+-------+-------+
	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
	#+----------------+-------+-------+-------+-------+
	#| Psi1Threshold  | 20A   | 20A   | 20A   | 20A   |
	#| Psi2Threshold  | 4A    | 5A    | 5A    | 5A    |
	#| Psi3Threshold  | 1A    | 1A    | 1A    | 1A    |
	#| Psi3Enable     | 1     | 1     | 1     | 1     |
	#| Psi4Enable     | 1     | 1     | 1     | 1     |
	#| ImonSlope      | 0     | 0     | 0     | 0     |
	#| ImonOffset     | 0     | 0     | 0     | 0     |
	#| IccMax         | 7A    | 34A   | 35A   | 35A   |
	#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
	#| AcLoadline(ohm)| 10.3m | 2.4m  | 3.1m  | 3.1m  |
	#| DcLoadline(ohm)| 10.3m | 2.4m  | 3.1m  | 3.1m  |
	#+----------------+-------+-------+-------+-------+
	#Note: IccMax settings are moved to SoC code
	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(4),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.voltage_limit = 1520,
	}"

	register "domain_vr_config[VR_IA_CORE]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.voltage_limit = 1520,
	}"

	register "domain_vr_config[VR_GT_UNSLICED]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.voltage_limit = 1520,
	}"

	register "domain_vr_config[VR_GT_SLICED]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.voltage_limit = 1520,
	}"

	# Send an extra VR mailbox command for the PS4 exit issue
	register "SendVrMbxCmd" = "2"

	# Enable SATA ports 1,2
	register "SataPortsEnable[0]" = "1"
	register "SataPortsEnable[1]" = "1"
	register "SataPortsEnable[2]" = "0"
	register "SataPortsDevSlp[0]" = "0"
	register "SataPortsDevSlp[1]" = "0"

	# Enable Root ports. 1-6 for LAN and Root Port 9
	register "PcieRpEnable[0]" = "1"
	register "PcieRpEnable[1]" = "1"
	register "PcieRpEnable[2]" = "1"
	register "PcieRpEnable[3]" = "1"
	register "PcieRpEnable[4]" = "1"
	register "PcieRpEnable[5]" = "1"
	register "PcieRpEnable[8]" = "1" # mPCIe WiFi

	# Enable Advanced Error Reporting for RP 1-6, 9
	register "PcieRpAdvancedErrorReporting[0]" = "1"
	register "PcieRpAdvancedErrorReporting[1]" = "1"
	register "PcieRpAdvancedErrorReporting[2]" = "1"
	register "PcieRpAdvancedErrorReporting[3]" = "1"
	register "PcieRpAdvancedErrorReporting[4]" = "1"
	register "PcieRpAdvancedErrorReporting[5]" = "1"
	register "PcieRpAdvancedErrorReporting[8]" = "1"

	# Enable Latency Tolerance Reporting Mechanism RP 1-6, 9
	register "PcieRpLtrEnable[0]" = "1"
	register "PcieRpLtrEnable[1]" = "1"
	register "PcieRpLtrEnable[2]" = "1"
	register "PcieRpLtrEnable[3]" = "1"
	register "PcieRpLtrEnable[4]" = "1"
	register "PcieRpLtrEnable[5]" = "1"
	register "PcieRpLtrEnable[8]" = "1"

	# Enable RP 9 CLKREQ# support
	register "PcieRpClkReqSupport[8]" = "1"
	# RP 9 uses CLKREQ0#
	register "PcieRpClkReqNumber[8]" = "0"

	# Clocks 0-5 for RP 1-6
	register "PcieRpClkSrcNumber[0]" = "0"
	register "PcieRpClkSrcNumber[1]" = "1"
	register "PcieRpClkSrcNumber[2]" = "2"
	register "PcieRpClkSrcNumber[3]" = "3"
	register "PcieRpClkSrcNumber[4]" = "4"
	register "PcieRpClkSrcNumber[5]" = "5"
	# RP 9 shares CLKSRC5# with RP 6
	register "PcieRpClkSrcNumber[8]" = "5"


	# USB 2.0 enable ports 1-8, disable ports 9-12
	register "usb2_ports[0]"  = "USB2_PORT_SHORT(OC_SKIP)"	# TYPE-A Port
	register "usb2_ports[1]"  = "USB2_PORT_SHORT(OC_SKIP)"	# TYPE-A Port
	register "usb2_ports[2]"  = "USB2_PORT_SHORT(OC_SKIP)"	# TYPE-A Port
	register "usb2_ports[3]"  = "USB2_PORT_SHORT(OC_SKIP)"	# TYPE-A Port
	register "usb2_ports[4]"  = "USB2_PORT_SHORT(OC_SKIP)"	# Type-A Port
	register "usb2_ports[5]"  = "USB2_PORT_SHORT(OC_SKIP)"	# TYPE-A Port
	register "usb2_ports[6]"  = "USB2_PORT_SHORT(OC_SKIP)"	# TYPE-A Port
	register "usb2_ports[7]"  = "USB2_PORT_SHORT(OC_SKIP)"	# mPCIe slot
	register "usb2_ports[8]"  = "USB2_PORT_EMPTY"		# Disabled
	register "usb2_ports[9]"  = "USB2_PORT_EMPTY"		# Disabled
	register "usb2_ports[10]" = "USB2_PORT_EMPTY"		# Disabled
	register "usb2_ports[11]" = "USB2_PORT_EMPTY"		# Disabled

	# USB 3.0 enable ports 1-4, disable ports 5-6
	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# TYPE-A Port
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# TYPE-A Port
	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# TYPE-A Port
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# TYPE-A Port
	register "usb3_ports[4]" = "USB3_PORT_EMPTY"		# Disabled
	register "usb3_ports[5]" = "USB3_PORT_EMPTY"		# Disabled

	register "SerialIoDevMode" = "{ \
		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled, \
		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled, \
		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled, \
		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled, \
		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled, \
		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled, \
		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled, \
		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
		[PchSerialIoIndexUart0] = PchSerialIoDisabled, \
		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
		[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
	}"

	# Lock Down CHIPSET_LOCKDOWN_COREBOOT
	register "common_soc_config" = "{
		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
	}"

	device cpu_cluster 0 on
		device lapic 0 on end
	end
	device domain 0 on
		device pci 00.0 on  end # Host Bridge
		device pci 02.0 on  end # Integrated Graphics Device
		device pci 08.0 off end # Gaussian Mixture Model
		device pci 13.0 off end # Integrated Sensor Hub
		device pci 14.0 on  end # USB xHCI
		device pci 14.1 off end # USB xDCI (OTG)
		device pci 14.2 off end # Thermal Subsystem
		device pci 14.3 off end # Camera I/O Host Controller
		device pci 15.0 off end # I2C #0
		device pci 15.1 off end # I2C #1
		device pci 15.2 off end # I2C #2
		device pci 15.3 off end # I2C #3
		device pci 16.0 on  end # Management Engine Interface 1
		device pci 16.1 off end # Management Engine Interface 2
		device pci 16.2 off end # Management Engine IDE-R
		device pci 16.3 off end # Management Engine KT Redirection
		device pci 16.4 off end # Management Engine Interface 3
		device pci 17.0 on  end # SATA
		device pci 19.0 off end # UART #2
		device pci 19.1 off end # I2C #5
		device pci 19.2 off end # I2C #4
		device pci 1c.0 on  end # PCI Express Port 1
		device pci 1c.1 on  end # PCI Express Port 2
		device pci 1c.2 on  end # PCI Express Port 3
		device pci 1c.3 on  end # PCI Express Port 4
		device pci 1c.4 on  end # PCI Express Port 5
		device pci 1c.5 on  end # PCI Express Port 6
		device pci 1c.6 off end # PCI Express Port 7
		device pci 1c.7 off end # PCI Express Port 8
		device pci 1d.0 on      # PCI Express Port 9 - WiFi
			smbios_slot_desc
				"SlotTypePciExpressMini52pinWithoutBSKO"
				"SlotLengthShort" "WIFI1" "SlotDataBusWidth1X"
		end
		device pci 1d.1 off end # PCI Express Port 10
		device pci 1d.2 off end # PCI Express Port 11
		device pci 1d.3 off end # PCI Express Port 12
		device pci 1e.0 off end # UART #0
		device pci 1e.1 off end # UART #1
		device pci 1e.2 off end # GSPI #0
		device pci 1e.3 off end # GSPI #1
		device pci 1e.4 off end # eMMC
		device pci 1e.5 off end # SDIO
		device pci 1e.6 off end # SDCard
		device pci 1f.0 on
			chip superio/ite/it8772f
				register "peci_tmpin" = "3"
				register "tmpin1_mode" = "THERMAL_RESISTOR"
				register "tmpin2_mode" = "THERMAL_RESISTOR"
				# FAN2 available on fan header but unused
				device pnp 2e.0 off end # FDC
				device pnp 2e.1 on # Serial Port 1
					io 0x60 = 0x3f8
					irq 0x70 = 4
				end
				device pnp 2e.4 on # Environment Controller
					io 0x60 = 0xa40
					io 0x62 = 0xa30
					irq 0x70 = 9
				end
				device pnp 2e.5 off end # Keyboard
				device pnp 2e.6 off end # Mouse
				device pnp 2e.7 off end # GPIO
				device pnp 2e.a off end # IR
			end
		end # LPC Interface
		device pci 1f.1 on  end # P2SB
		device pci 1f.2 on  end # Power Management Controller
		device pci 1f.3 off end # Intel HDA
		device pci 1f.4 on  end # SMBus
		device pci 1f.5 off end # PCH SPI
		device pci 1f.6 off end # GbE
	end
end