blob: f1681384a87d52d6c7f842b2ce9a59a90ca7b589 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
void mainboard_late_rcba_config(void)
{
u32 reg32;
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
/* Disable PCI bridge so MRC does not probe this bus */
reg32 |= PCH_DISABLE_P2P;
RCBA32(FD) = reg32;
}
int mainboard_should_reset_usb(int s3resume)
{
return !s3resume;
}
|
