blob: 4c8be412cf0e818cf75545f7a749d1820cfbe6aa (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
|
config BOARD_SUNW_ULTRA40
bool "Ultra 40"
select ARCH_X86
select CPU_AMD_SOCKET_940
select NORTHBRIDGE_AMD_AMDK8
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_CK804
select SUPERIO_SMSC_LPC47M10X
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
select USE_DCACHE_RAM
select HAVE_HARD_RESET
select IOAPIC
select BOARD_ROMSIZE_KB_1024
config MAINBOARD_DIR
string
default sunw/ultra40
depends on BOARD_SUNW_ULTRA40
config DCACHE_RAM_BASE
hex
default 0xcf000
depends on BOARD_SUNW_ULTRA40
config DCACHE_RAM_SIZE
hex
default 0x01000
depends on BOARD_SUNW_ULTRA40
config APIC_ID_OFFSET
hex
default 0x10
depends on BOARD_SUNW_ULTRA40
config K8_REV_F_SUPPORT
bool
default n
depends on BOARD_SUNW_ULTRA40
config SB_HT_CHAIN_ON_BUS0
int
default 2
depends on BOARD_SUNW_ULTRA40
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
depends on BOARD_SUNW_ULTRA40
config LB_CKS_RANGE_END
int
default 122
depends on BOARD_SUNW_ULTRA40
config LB_CKS_LOC
int
default 123
depends on BOARD_SUNW_ULTRA40
config MAINBOARD_PART_NUMBER
string
default "Ultra 40"
depends on BOARD_SUNW_ULTRA40
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
depends on BOARD_SUNW_ULTRA40
config MAX_CPUS
int
default 4
depends on BOARD_SUNW_ULTRA40
config MAX_PHYSICAL_CPUS
int
default 2
depends on BOARD_SUNW_ULTRA40
config HT_CHAIN_END_UNITID_BASE
hex
default 0x0
depends on BOARD_SUNW_ULTRA40
config HT_CHAIN_UNITID_BASE
hex
default 0x0
depends on BOARD_SUNW_ULTRA40
config USE_INIT
bool
default n
depends on BOARD_SUNW_ULTRA40
config SB_HT_CHAIN_ON_BUS0
int
default 2
depends on BOARD_SUNW_ULTRA40
config IRQ_SLOT_COUNT
int
default 11
depends on BOARD_SUNW_ULTRA40
|
