summaryrefslogtreecommitdiff
path: root/src/mainboard/sunw/ultra40/devicetree.cb
blob: 059724ee37c708f8307cb4cd03aca58703236b0c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
chip northbridge/amd/amdk8/root_complex		# Root complex
  device lapic_cluster 0 on			# (L)APIC cluster
    chip cpu/amd/socket_940			# CPU socket
      device lapic 0 on end			# Local APIC of the CPU
    end
  end
  device pci_domain 0 on			# PCI domain
    chip northbridge/amd/amdk8			# Northbridge / RAM controller
      device pci 18.0 on end
      device pci 18.0 on			# Link 0 == LDT 0
        chip southbridge/nvidia/ck804		# Southbridge
          device pci 0.0 on end			# HT
          device pci 1.0 on			# LPC
            chip superio/smsc/lpc47m10x		# Super I/O
              device pnp 2e.0 off		# Floppy
                io 0x60 = 0x3f0
                irq 0x70 = 6
                drq 0x74 = 2
              end
              device pnp 2e.3 off		# Parallel port
                io 0x60 = 0x378
                irq 0x70 = 7
              end
              device pnp 2e.4 on		# Com1
                io 0x60 = 0x3f8
                irq 0x70 = 4
              end
              device pnp 2e.5 off		# Com2
                io 0x60 = 0x2f8
                irq 0x70 = 3
              end
              device pnp 2e.7 off		# PS/2 keyboard
                io 0x60 = 0x60
                io 0x62 = 0x64
                irq 0x70 = 1
                irq 0x72 = 12
              end
            end
          end
          device pci 1.1 on			# SM 0
            chip drivers/generic/generic	# DIMM 0-0-0
              device i2c 50 on end
            end
            chip drivers/generic/generic	# DIMM 0-0-1
              device i2c 51 on end
            end
            chip drivers/generic/generic	# DIMM 0-1-0
              device i2c 52 on end
            end
            chip drivers/generic/generic	# DIMM 0-1-1
              device i2c 53 on end
            end
            chip drivers/generic/generic	# DIMM 1-0-0
              device i2c 54 on end
            end
            chip drivers/generic/generic	# DIMM 1-0-1
              device i2c 55 on end
            end
            chip drivers/generic/generic	# DIMM 1-1-0
              device i2c 56 on end
            end
            chip drivers/generic/generic	# DIMM 1-1-1
              device i2c 57 on end
            end
          end
          device pci 1.1 on			# SM 1
            # PCI device SMBus address will
            # depend on addon PCI device, do
            # we need to scan_smbus_bus?
            # chip drivers/generic/generic	# PCIXA slot 1
            #   device i2c 50 on end
            # end
            # chip drivers/generic/generic	# PCIXB slot 1
            #   device i2c 51 on end
            # end
            # chip drivers/generic/generic	# PCIXB slot 2
            #   device i2c 52 on end
            # end
            # chip drivers/generic/generic	# PCI slot 1
            #   device i2c 53 on end
            # end
            # chip drivers/generic/generic	# Master CK804 PCI-E
            #   device i2c 54 on end
            # end
            # chip drivers/generic/generic	# Slave CK804 PCI-E
            #   device i2c 55 on end
            # end
            chip drivers/generic/generic	# MAC EEPROM
              device i2c 51 on end
            end
          end
          device pci 2.0 on end			# USB 1.1
          device pci 2.1 on end			# USB 2
          device pci 4.0 on end			# ACI
          device pci 4.1 off end		# MCI
          device pci 6.0 on end			# IDE
          device pci 7.0 on end			# SATA 1
          device pci 8.0 on end			# SATA 0
          device pci 9.0 on end			# PCI
          device pci a.0 on end			# NIC
          device pci b.0 off end		# PCI E 3
          device pci c.0 off end		# PCI E 2
          device pci d.0 off end		# PCI E 1
          device pci e.0 on end			# PCI E 0
          register "ide0_enable" = "1"
          register "ide1_enable" = "1"
          register "sata0_enable" = "1"
          register "sata1_enable" = "1"
          # 1: SMBus under 2e.8, 2: SM0 3: SM1
          register "mac_eeprom_smbus" = "3"
          register "mac_eeprom_addr" = "0x51"
        end
      end
      device pci 18.0 on end			# Link 2
      device pci 18.1 on end
      device pci 18.2 on end
      device pci 18.3 on end
    end
    chip northbridge/amd/amdk8			# Northbridge / RAM controller
      device pci 19.0 on end			# Link 0
      device pci 19.0 on			# Link 1 == LDT 1
        chip southbridge/nvidia/ck804		# Southbridge
          device pci 0.0 on end			# HT
          device pci 1.0 on end			# LPC
          device pci 1.1 off end		# SM
          device pci 2.0 off end		# USB 1.1
          device pci 2.1 off end		# USB 2
          device pci 4.0 off end		# ACI
          device pci 4.1 off end		# MCI
          device pci 6.0 off end		# IDE
          device pci 7.0 off end		# SATA 1
          device pci 8.0 off end		# SATA 0
          device pci 9.0 off end		# PCI
          device pci a.0 on end			# NIC
          device pci b.0 off end		# PCI E 3
          device pci c.0 off end		# PCI E 2
          device pci d.0 off end		# PCI E 1
          device pci e.0 on end			# PCI E 0
          # 1: SMBus under 2e.8, 2: SM0 3: SM1
          register "mac_eeprom_smbus" = "3"
          register "mac_eeprom_addr" = "0x51"
        end
      end
      device pci 19.0 on end
      device pci 19.1 on end
      device pci 19.2 on end
      device pci 19.3 on end
    end
  end
end