summaryrefslogtreecommitdiff
path: root/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
blob: 317d643d9a3372b1ab878b8d213f77b1eeed12c9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
chip northbridge/amd/amdfam10/root_complex	# Root complex
	device cpu_cluster 0 on			# (L)APIC cluster
		chip cpu/amd/socket_F_1207	# CPU socket
			device lapic 0 on end	# Local APIC of the CPU
		end
	end
	device domain 0 on			# PCI domain
		subsystemid 0x15d9 0x1511 inherit
		chip northbridge/amd/amdfam10	# Northbridge / RAM controller
			device pci 18.0 on end
			device pci 18.0 on end
			device pci 18.0 on	# SB on link 2
				chip southbridge/nvidia/mcp55		# Southbridge
					device pci 0.0 on end			# HT
					device pci 1.0 on			# LPC
						chip superio/winbond/w83627hf	# Super I/O
							device pnp 2e.0 off	# Floppy
								io 0x60 = 0x3f0
								irq 0x70 = 6
								drq 0x74 = 2
							end
							device pnp 2e.1 off	# Parallel port
								io 0x60 = 0x378
								irq 0x70 = 7
							end
							device pnp 2e.2 on	# Com1
								io 0x60 = 0x3f8
								irq 0x70 = 4
							end
							device pnp 2e.3 off	# Com2
								io 0x60 = 0x2f8
								irq 0x70 = 3
							end
							device pnp 2e.5 on	# PS/2 keyboard
								io 0x60 = 0x60
								io 0x62 = 0x64
								irq 0x70 = 1
								irq 0x72 = 12
							end
							device pnp 2e.6 off	# SFI
								io 0x62 = 0x100
							end
							device pnp 2e.7 off	# GPIO, game port, MIDI
								io 0x60 = 0x220
								io 0x62 = 0x300
								irq 0x70 = 9
							end
							device pnp 2e.8 off end	# WDTO PLED
							device pnp 2e.9 off end	# GPIO SUSLED
							device pnp 2e.a off end	# ACPI
							device pnp 2e.b on	# Hardware monitor
								io 0x60 = 0x290
								irq 0x70 = 5
							end
						end
					end
					device pci 1.1 on end
					device pci 1.1 on			# SM 1
						# PCI device SMBus address will
						# depend on addon PCI device, do
						# we need to scan_smbus_bus?
						chip drivers/generic/generic	# MAC EEPROM
							device i2c 51 on end
						end
					end
					device pci 2.0 on end	# USB 1.1
					device pci 2.1 on end	# USB 2
					device pci 4.0 on end	# IDE
					device pci 5.0 on end	# SATA 0
					device pci 5.1 on end	# SATA 1
					device pci 5.2 on end	# SATA 2
					device pci 6.1 off end	# AZA
					device pci 7.0 on
						device pci 1.0 on end
					end
					device pci 8.0 off end
					device pci 9.0 off end
					device pci a.0 on end	# PCI E 5
					device pci b.0 on end	# PCI E 4
					device pci c.0 on end	# PCI E 3
					device pci d.0 on end	# PCI E 2
					device pci e.0 on end	# PCI E 1
					device pci f.0 on end	# PCI E 0
					register "ide0_enable" = "1"
					register "sata0_enable" = "1"
					register "sata1_enable" = "1"
					# 1: SMBus under 2e.8, 2: SM0 3: SM1
					register "mac_eeprom_smbus" = "3"
					register "mac_eeprom_addr" = "0x51"
				end
			end
			device pci 18.1 on end
			device pci 18.2 on end
			device pci 18.3 on end
			device pci 18.4 on end
			device pci 19.0 on end
			device pci 19.0 on end
			device pci 19.0 on
				chip southbridge/amd/amd8132
					device pci 0.0 on end
					device pci 0.1 on end
					device pci 1.0 on
						device pci 3.0 on end
						device pci 3.1 on end
					end
					device pci 1.1 on end
				end
			end
			device pci 19.1 on end
			device pci 19.2 on end
			device pci 19.3 on end
			device pci 19.4 on end
		end
	end
end